Row grabbing system

ABSTRACT

A real time frame grabbing system for substantially instantaneously providing a continuous video display of a selectably predetermined video frame of information on a video display means from continuously transmittable video information which is transmitted as a plurality of pseudo video scan lines wherein the selected frame being grabbed is updateable on a displayable-row-by-displayable-row basis. Each of the pseudo video scan lines has a television scan line format and comprises a complete self-contained packet of digital information sufficient to provide an entire displayable row of video data characters, the pseudo video scan line having an associated transmission time equivalent to that of a television video scan line. The packet of digital information comprises at least address information for a displayable row and data information for the displayable characters in the row. Each of these pseudo video scan lines further comprises a horizontal sync signal at the beginning thereof and a start bit pulse between the horizontal sync signal and the packet of digital information. The start bit pulse provides a unique synchronizing pulse for each transmitted pseudo video scan line for enabling precise determination of a sampling time for the received distributed pseudo video scan line to enable accurate determination of the binary state of the bits comprising the digital information packet, with the receiver being responsive to the occurrence of the start bit for each distributed pseudo video scan line for providing a reset signal for resetting the signal processing means in response to detection of the start bit to provide enhanced noise immunity and accurate signal information. The pseudo video scan lines are both transmitted and received through a conventional television distribution system. If desired, a local micro-processor may be utilized to control the functions of the receiver terminal and may be used in conjunction with a printer interface to enable both continuous high speed video display and real time pick off for hard copy printing.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is an improvement on the row grabbing system describedin our previous U.S. Pat. No. 3,889,054, issued June 10, 1975 and isrelated to the commonly assigned copending U.S. patent application ofRobert H. Nagel, entitled "Information Retrievable System HavingSelectable Purpose Variable Function Terminal", filed Sept. 10, 1975,and bearing U.S. Ser. No. 611,927, .Iadd.now U.S. Pat. No. 4,064,490,issued Dec. 20, 1977, .Iaddend.the contents of both of which arespecifically incorporated by reference herein.

BACKGROUND OF THE INVENTION

The present invention relates to video communication systems in whichindividual frames may be grabbed for video display thereof.

DESCRIPTION OF THE PRIOR ART

Video communication systems in which individual frames may be grabbedfor video display are well known, such as the system disclosed in U.S.Pat. No. 3,740,465 or a system employing the Hitachi frame grabbingdisc. These prior art systems such as the one disclosed in U.S. Pat. No.3,746,780 are normally two-way request response systems requiring theuser to request information by the dialing of a specific digital codewhich is uniquely assigned to each frame. However, such systems normallygrab a group of frames for storage and then subsequently select theindividual frame for display out of the group of grabbed frames asopposed to instantaneously selecting a single frame in real time.Furthermore, such prior art systems do not provide for real timeupdating of the grabbed video frame. Furthermore, some such prior artframe grabbing systems, such as the type disclosed in U.S. Pat. No.3,397,283, are normally capable of only grabbing the next immediatesignal in resonse to the provision of a starter signal or, as disclosedin U.S. Pat. No. 3,051,777, utilize a counter for frame location whichmust be reset to the beginning of a tape for video tape suppliedinformation in order to locate a selected frame to be grabbed. Thesesystems are not applicable in a real time frame grabbing environment.Similarly, other typical prior art frame grabbing systems, such asdisclosed in U.S. Pat. Nos. 3,695,565; 2,955,197; 3,509,274; 3,511,929and 3,582,651, can not be utilized in a real time frame grabbingenvironment, such as one in which the video information associated withthe grabbed frame is capable of being continuously updated. Accordingly,presently available prior art frame grabbing systems familiar to theInventors are not capable of easily locating a frame to be grabbed inreal time nor of being able to continuously update such a grabbed framein real time.

Video communication systems in which the signal being transmitted isdigitized are also well known. For example, U.S. Pat. No. 3,743,767discloses a video communication system for the transmission of digitaldata over standard television channels wherein the digital data istransmitted in a conventional television scan line format throughconventional television distribution equipment. However, such a priorart communication system merely digitizes one television scan line at atime for distribution to a video display terminal on a bit-by-bit basisin a line, 84 bits of information being provided per television scanline. Furthermore, such a prior art system is not transmissionselectable by every display terminal nor is the data for a displayablevideo row packed into a self-contained pseudo video scan lineinformation packet. Thus, there is no significant increase in the datatransmission rate resulting from such a prior art video communicationsystem. Similarly, U.S. Pat. No. 3,061,672 and 3,569,617 and German Pat.No. 2,307,414 are examples of other prior art video communicationsystems in which television signals are digitized without anysignificant resultant compression in data transmission time.Furthermore, these other prior art systems require special distributioncircuitry. In addition, prior art video communication system in which adigital television signal is transmitted do not sufficiently isolate theindividual rows comprising a frame so as to provide satisfactory noiseimmunity between these rows nor is there satisfactory data compressionin the transmission time of the video information in such prior artsystems nor satisfactory distortion compensation. These disadvantages ofthe prior art are overcome by the present invention.

SUMMARY OF THE INVENTION

A real time frame grabbing system for substantially instantaneouslyproviding a continuous video display of a selectable predetermined videoframe of information on a video display means from continuouslytransmittable video information, wherein such information is transmittedas a plurality of pseudo video scan lines is provided. Each of thepseudo video scan lines has a television video scan line format andcomprises a complete self-contained packet of digital informationsufficient to provide an entire displayable row of video datacharacters, the pseudo video scan line having an associated transmissiontime equivalent to that of a television video scan line. The packet ofdigital information comprises at least address information, such aspage, group, permission, user and direct address for a displayable rowand data information for the displayable characters, such as 32characters or 64 characters, in a displayable row. Each of the pseudovideo scan lines further comprises a horizontal sync signal at thebeginning thereof, each horizontal sync signal providing a recordseparator between adjacent pseudo video scan lines, and a start bitpulse between the horizontal sync signal and the packet of digitalinformation. The transmitter for the pseudo video scan lines includesmeans for providing a vertical sync signal after a predeterminedplurality of pseudo video scan lines have been transmitted, the pseudovideo scan line being a composite video signal. These transmitted pseudovideo scan line composite video signals are distributed through aconventional television distribution system, such as a cabledistribution system, for various video display means for providing acontinuous video display thereof. The receiver which is operativelyconnected between the distribution network and an associated videodisplay means, processes the distributed composite pseudo video scanline signals and provides a displayable video row to the associatedvideo display means from each of the pseudo video scan line signalspertaining to the frame selected in order to provide the continuousvideo display, a predetermined plurality of displayable video rowscomprising a displayable video frame of information. The receiver alsopreferably includes means for updating the continuously videodisplayable selectable frame on a displayable video row-by-row basisdependent on the real time data information content of the receivedpseudo video scan line. The start bit pulse provides a uniquesynchronizing pulse for each transmitted pseudo video scan line forenabling precise determination of a sampling time for the receiveddistributed pseudo video scan line to enable accurate determination ofthe binary state of the bits comprising the digital information packet.The receiver signal processing means comprises means responsive to theoccurrence of the start bit for each distributed pseudo video scan linefor providing a reset signal for resetting the processing means inresponse to detection of the start bit for enhancing noise immunity andaccurate signal information detection.

Each of the packets of digital information contained within the pseudovideo scan line also preferably includes an error check informationcontent with the receiver including error check means for obtaining anerror check indication of the distributed associated pseudo video scanline on a word-by-word basis as opposed to a bit-by-bit basis. Thereceiver also includes condition responsive means for preventing theprovision of the displayable video row from the associated pseudo videoscan line when a predetermined output condition is not met.

The system also preferably includes programmable means, such as ageneral purpose computer, for receiving the continuously transmittablevideo information, retrievably storing this information, reformatting itinto a desired pseudo video scan line format and continuously providingthis reformatted information to the transmitter on a word-by-word basis,a word comprising a pair of displayable characters. Furthermore, theprogrammable means preferably includes means for interleaving thereformatted pseudo video scan line information to provide pseudo videoscan line information corresponding to a common assigned row for aplurality of frames to the transmitter before providing pseudo videoscan line information corresponding to a subsequent different commonassigned row for the plurality of frames to the transmitter. Thus, theprovision of the pseudo video scan line enables the use of conventionaltelevision transmission techniques and equipment for transmission andreception as well as conventional television circuitry for processingthe received and transmitted signals. Furthermore, by utilizing thehorizontal sync as a record separator, one can insure that any loss ofsynchronization or noise pulse will not disrupt more information thanone pseudo video scan line. In addition, significant data compression intransmission time is otained by transmitting the pseudo video scan linesas opposed to conventional television scan lines, with each pseudo videoscan line being self-contained packet of information sufficient fordisplay of an entire displayable video row containing a plurality ofconventional television scan lines, such as 13, as opposed to display ofone television scan line. Each receiver may preferably be controlled bya local microprocessor which, if desired, in addition to controlling therow-by-row display and updating of information may be utilized inconjunction with a computer/printer interface for enabling continuoushigh speed video display of the information with real time pick off ofthis information, where desired, for "hard copy" printing thereof. Thelocal microprocessor which operates in conjunction with a keyboard whichprovides the information request, enables updating on a row-by-row basisas opposed to a Page-by-page or frame-by-frame basis as new informationis provided in real time, the selected frame being automatically updatedin real time as new information is provided for a given row of thedisplayed selected frame.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagrammatic illustration of a typical pseudo video scanline format in accordance with our previous U.S. Pat. No. 3,889,054;

FIG. 2 is a diagrammatic illustration of a typical pseudo video scanline format in accordance with the present invention;

FIG. 3 is a graphical illustration of conventional vertical drive andcomposite sync signals illustrating the origin of the vertical syncsignal in accordance with the present invention;

FIG. 4 is a block diagram of the phase locked loop portion of thearrangement illustrated in FIG. 5;

FIG. 5 is a block diagram of the timing control, memory input controland a part of the output processing portions of the preferred receiverof the present invention;

FIG. 6 is a block diagram of another portion of the memory input controlportion of the preferred receiver of the present invention;

FIG. 7 is a block diagram of the memory and output processing portion ofthe preferred receiver of the present invention;

FIG. 7A is a graphical illustration of the timing associated withvarious signals in the arrangement of FIG. 7;

FIG. 8 is a logic diagram, partially in schematic, of a portion of thetiming and keyboard control portion of the preferred receiver of thepresent invention illustrated in FIG. 5;

FIG. 9 is a block diagram of another portion of the memory and outputprocessing portion of the preferred receiver of the present invention;

FIG. 10 is a logic diagram, partially in schematic, of the keyboardportion of the timing and keyboard control portion of the receiverillustrated in FIG. 5;

FIG. 11 is a logic diagram, partially in schematic, of the portion ofthe memory input control portion of the receiver illustrated in FIG. 6;

FIG. 12 is a logic diagram, partially in schematic, of the portion ofthe memory input control portion of the receiver illustrated in FIG. 7;

FIG. 13 is a logic diagram, partially in schematic, of the memory andoutput processing portion of the receiver illustrated in FIG. 5;

FIG. 14 is a logic diagram, partially in schematic, of another portionof the memory and output processing portion of the receiver illustratedin FIG. 5;

FIG. 15 is a block diagram of the preferred transmitter portion of thepresent inention;

FIG. 16 is a logic diagram of the first in-first out memory portion ofthe transmitter portion illustrated in FIG. 15;

FIGS. 17 and 18 are logic diagrams, partially in schematic, of thetransmitter portion illustrated in FIG. 15 except for the first in-firstout memory portion illustrated in FIG. 16;

FIG. 19 is a functional block diagram of the preferred embodiment of therow grabbing system of the present invention;

FIG. 20 is a schematic diagram of the video processor portion of thepreferred receiver of the present invention illustrated in FIG. 5;

FIGS. 21A, 21B and 21C are graphic illustrations of the variouswaveforms present throughout the video processor of FIG. 20;

FIG. 22 is a logic diagram, partially in schematic, of another portionof the video processor portion of the receiver illustrated in FIGS. 5and 20;

FIG. 22A is a graphic illustration of the various waveforms present inthe video processor portion illustrated in FIG. 22;

FIG. 23 is a block diagram of the various interconnections orinterfacings of the video processor of FIGS. 20 and 22 with the balanceof the circuitry in the preferred receiver of the present invention;

FIG. 24 is a block diagram, partially in schematic, of the variousinterface connections between the microprocessor and the keyboard in thepreferred receiver of the present invention;

FIG. 25 is a block diagram, partially in schematic, of thecomputer/printer interface portion of the preferred receiver of thepresent invention illustrated in FIG. 26;

FIG. 26 is a block diagram of the preferred receiver of the presentinvention including a functional indication of the various controlsignals utilized therein;

FIG. 27 is a block diagram of the microprocessor portion of thepreferred receiver of the present invention illustrated in FIG. 26;

FIG. 28 is a functional block diagram similar to FIG. 27 for use inexplaining an exemplary program for the microprocessor of the preferredreceiver of the present invention;

FIG. 29 is a diagrammatic illustration of a video display screen forproviding 32 and/or 64 character display selection; and

FIG. 30 is a fragmentary block diagram, partially in schematic, of anadditional portion of the memory and output processing portion of thereceiver illustrated in FIG. 13 for providing 32 and/or 64 characterselection.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS General SystemDescription

Referring now to the drawings in detail and initially to FIG. 19thereof, the preferred embodiment of the row grabbing system, generallyreferred to by the reference numeral 10, described in our previouslyissued U.S. Pat. No. 3,889,054, of which the foregoing invention is animprovement thereon is shown. As shall be described in greater detailhereinafter, the general system description of the present invention isessentially similar to that previously given in the aforementioned U.S.Pat. No. 3,889,054 with the exception that the present improved rowgrabbing system preferably utilizes a microcomputer control in thereceiver portion in place of some of the hard-wiring control functionsperformed by the row grabbing system described in U.S. Pat. No.3,889,054. For purposes of clarity, where applicable, the appropriatepertinent portions of the row grabbing system described in our U.S. Pat.No. 3,889,054 will be reiterated herein, the balance of the applicabledescription therein being specifically incorporated by reference herein.The row grabbing system 10 of the present invention is preferably aone-way frame grabbing system in which continuously transmittedinformation or messages are transmitted via pseudo video scan lines 12a,illustrated in FIGS. 2 and 3, on a row-by-row basis, with the pseudovideo scan line 12a preferably being identical in format to aconventional video scan line; that is, it is consistent with FCC and EIAstandards for a video scan line signal format. However, this pseudovideo scan line 12a actually contains a row of information such asapproximately between 11 and 13 actual television video scan lines ofinformation, with the transmission time of the pseudo video scan line12a preferably being equal to the transmission time of a conventional TVvideo scan line, which is approximately 63 microseconds. The variousportions of the pseudo video scan line 12a will be described in greaterdetail hereinafter with reference to FIGS. 2 and 3 and it should benoted at this time that the format for the preferred pseudo video scanline 12a of the present invention is similar, with certain exceptions tobe described hereinafter, to the previously preferred format for thepseudo video scan line 12, illustrated in FIG. 1, which was described inour previously issued U.S. Pat. No. 3,889,054, with identical regionsthereon being given the same reference designations. As was shown inthat patent, in the row grabbing system 10 of the present invention, theinformation is updated on a row-by-row basis by transmission of a pseudovideo scan line containing new information so that the frame beinggrabbed will effectively have this row containing new informationupdated when this row of information is updated in memory. In thepreferred system 10 of the present invention, as well as in the systemdescribed in U.S. Pat. No. 3,889,054, continuously transmittedinformation or messages may be instantaneously "grabbed" in real time soas to repetitively provide a video display of a selected video frame ofsuch information which may be updated on a row-by-row basis in realtime.

Video information may be of any conventional type, such as newsinformation, money rate information, stock market information, localadvertising, television program listings, weather information, consumerinformation, etc., which is conventionally supplied from conventionalexternal information sources for such types of information, such assources 2002 and 2004 shown by way of example. These conventionalexternal information sources 2002 and 2004 preferably conventionallysupply this information in a digital format such as from a ticker fornews information or stock information, by way of example, through aconventional communication line 2006 or 2008 or a conventional localvideo terminal, preferably, to a conventional minicomputer 2000, such asmodel No. PDP-8e manufactured by Digital Equipment Corp. Minicomputer2000 preferably has an associated conventional mass memory 2010 forconventional storage of data. Computer 2000 stores this information inmass memory 2010, reformats it, such as by adding other information, andcontinuously provides this information as a 12 bit parallel output 2011to a transmitter 20, to be described in greater detail hereinafter,which provides the pseudo video scan line 12a for transmission to the TVdistribution network. It should be noted that at any time, the 12 bitparallel output of computer 2000 preferably presents two characters forone word. If desired, a 14 bit parallel output from the computer 2000could be utilized to provide two 7 bit characters. The mass memory 2010is preferably updated by the computer 2000 in conventional fashion atthe optimum transfer time for data which is, conventionally, notnecessarily in the order of the reception of the external informationfrom sources 2002 and 2004, this data being preferably continuouslysuppliable in real time to the computer 2000. In conventional fashion,information in computer 2000 is supplied to the transmitter 20 which, inturn, supplies this information to a CATV cable system 22 through aconventional RF modulator 24, composite video being supplied tomodulator 24 from transmitter 20. One such modulator 24 is preferablyprovided for each television channel on which information is to betransmitted, only one such channel being illustrated in FIG. 15 by wayof example. Preferably, the mass memory 2010 which is read inconventional fashion by computer 2000 to provide the requisiteinformation via transmitter 20 to the CATV cable system 22, hassufficient storage capacity to store the entire page capacity of thesystem.

As used hereinafter throughout the specification and claims, the term"page" means one video frame of information, the term "group" means apredetermined number of pages, the term "row" is a displayable video rowand means a portion of a page containing a plurality of conventionaltelevision video scan lines, the term "pseudo video scan line" means asignal which is identical in form to that of a conventional video scanline but which actually contains a row of information, such asapproximately between 11 and 13 actual television video scan lines ofinformation with the transmission time of the pseudo video scan linebeing equal to the transmission time of a conventional TV video scanline and with the pseudo video scan line being an entire packet ofinformation necessary for video display of that row. The termconventional or television video scan line is used in the conventionalmanner.

As described in our previously issued U.S. Pat. No. 3,889,054, the massmemory 2010 can be any conventional mass memory stage device sufficientto store the requisite page capacity of the system, such as an RK-08memory device manufactured by Digital Equipment Corp. The output of thecomputer 2000 is preferably conventionally transmitted from computer2000 to the transmitter 20 via conventional data break of the computer2000. All pages of information are preferably continuously beingtransmitted from the computer 2000 through transmitter 20 on apseudo-video-scan-line-by-pseudo-video-scan-line basis, that isrespectively on a row-by-row basis, through the appropriate RF modulator24 for the video channel being utilized and therefrom, through the CATVcable system 22 to conventional video display terminals or devices 2013and 2015, such as commercially available video monitors, two suchdevices being shown by way of example. It should be noted that thenumber of video display devices 2013 and 2015 preferably have norequisite correlation with the number of external information sources2002 and 2004 and more such sources could be utilized than video displaydevices or vice versa if desired. In normal contemplated use, the numberof video display devices 2013 and 2015 will normally exceed the numberof external information sources 2002 and 2004, however, this need not bethe case. The computer 2000 conventionally recirculates the dataprovided thereto in continuous fashion and, as previously mentioned,eventually updates the mass memory 2010 at the optimum transfer time forthe data, which time is not necessarily in the order or reception of theexternal information from sources 2002 and 2004. The information fromexternal sources 2002 and 2004, which is preferably being providedsubstantially continuously to the computer 2000 (as long as it beinggenerated from the external sources 2002 and 2004) is provided to themass memory 2010 and instantaneously to the transmitter 20 whichoperates in a manner to be described in greater detail hereinafter toprovide the pseudo video scan line 12a transmission of the information.Each video display device 2013 and 2015 preferably has an associateddisplay control unit 25 and 26, respectively, which preferably functionsto enable the real time frame grabbing or selection of a single page ofcontinuously transmitted information for the instantaneous repetitivecontinuous video display, or frame grabbing thereof, this informationbeing updatable on a row-by-row basis in real time. Preferably, each ofthe display control units 25 and 26 by way of example, one such displaycontrol unit preferably being associated with each video displayterminal device, are identical in structure and operation. If desired,however, any display control unit 25-26 may be modified in a manner,such as described in U.S. Pat. No. 3,889,054, so as to prevent thereception of certain categories of informaion while enabling thereception of other categories of information. For purposes of clarity,only one such typical display control unit 25 will be described by wayof example, the structure and operation previously mentioned, beingidentical with that of display control unit 26. Identical referencenumerals, followed by the letter a will be utilized in FIG. 19 forelements of display control unit 26 which are identical in structure andoperation with those of display control unit 25. In the overall systemblock diagram of FIG. 19, the display control unit 25 preferablycontains a conventional RF demodulator 27, one such RF demodulator 27being provided for each channel and a receiver 28, to be described ingreater detail hereinafter, which receiver preferably includes amicrocomputer and which receives the composite video demodulated bydemodulator 27 and determines whether the use is correct, the user haspermission to receive the pseudo video scan line information beingtransmitted at that time, whether the signal is error free, whether thepage address of the pseudo video scan line is correct, and whether adirect address condition exists, and, preferably, assuming the pseudovideo scan line signal passes all these tests, then the receiverprocesses this signal and provides a video signal corresponding to adisplayable row of information on the video display device 2013.

Referring now to FIGS. 4 through 14, 20 through 23, and once again toFIGS. 2 and 3, the preferred improved receiver portion 28 of theimproved row grabbing system 10 of the present invention shall bedescribed in greater detail. As will be described with reference to thepreferred transmitter portion 20 of the row grabbing system 10 of thepresent invention, the transmitter 20 preferably provides the pseudovideo scan line such as the type 12a illustrated in FIG. 1. This pseudovideo scan line 12a, as was previously described, is identical in formatto a conventional video scan line; that is, it is consistent with FCCand EIA standards for video scan line signal format; however this pseudovideo scan line 12a actually contains a row of information, such asapproximately between 11 and 13 actual television video scan lines ofinformation with the transmission time of the pseudo video scan line 12abeing equal to the transmission time of a conventional TV video scanline, whichis approximately 63 microseconds. With respect to the pseudovideo scan line 12a, the horizontal sync and vertical sync portions arepreferably identical to a conventional video signal as is the format forthe horizontal sync and the vertical sync as well as the horizontal syncamplitude. The time and amplitude envelope of the video region of thepseudo video scan line 12a, which region is defined as areas H, J, B, C,D, E, and K in FIG. 2, is identical with the format for a conventionalvideo scan line as is the three dimensional frequency envelope. Thus,all of the above mentioned standard conditions for a conventional videoscan line signal are met by the pseudo video scan line 12a provided bythe transmitter portion 20 of the improved row grabbing system 10 of thepresent invention and received by the improved receiver portion 28.Accordingly, any equipment that can handle conventional video can handlethe pseudo video scan line 12a of the present invention which can thusbe transmitted and received through a conventional televisiondistribution system with conventional television equipment.

Returning once again to the pseudo video scan line 12a illustrated inFIG. 2, as is also true for the pseudo video scan line 12 illustrated inFIG. 1 which was previously described in our U.S. Pat. No. 3,889,054,the signal received by the receiver portion 28 and transmitted bytransmitter 20 is in reality a digital signal which looks like aconventional video scan line to the receiver 28. Pseudo video scan line12a, as will be described in greater detail hereinafter, however,preferably employs a start bit to provide timing and phase adjustmentfor the phase locked loop of the receiver terminal 28. In such aninstance, region F which was previously contained in the pseudo videoscan line 12 trasmitted in the system of our U.S. Pat. No. 3,889,054,and which contained the clock synchronizing burst or pulse train at thebit rate (the frequency preferably being equal to one-half the bit rate)and comprised a pulse train of ones and zeros for two character spacesor 14 bits, is not present and the sync burst information which waspreviously contained therein is not required for timing and phaseadjustment in the improved row grabbing system of the present invention.Instead, region H, which preferably contains color burst information andregion J which preferably contains one start bit are preferably insertedbetween regions A and B, with regions B, C, D, and E beingelectronically shifted down in position to be adjacent region G, onlybeing separated therefrom by a region K, which region K merelyrepresents the standard TV spacing for providing the front porch of thesignal, the back porch of the signal being defined between region A andthe leading edge of the start bit in region J. The color burst signal inregion H preferably is the standard FCC eight cycle signal at 3.58megahertz. Apart from the repositioning and deletion of certain regionsof the pseudo video scan line 12 of FIG. 1, the contents of regions A,B, C, D, E and G in pseudo video scan line 12a of FIG. 2 is preferablyidentical with that previously described with reference to FIG. 1 in ourU.S. Pat. No. 3,889,054 with respect to the transmission of a dislayablerow of data. Suffice it to say for purposes of clarity, that region Arepresents the horizontal sync signal which indicates the beginning ofthe pseudo video scan line from the beginning of the horizontal sweepfor a conventional television scan line; and region B represents thepseudo video scan line 12a address which contains all the followinginformation bit locations, a one preferably indicating the presence of apulse and a zero preferably indicating the absence of a pulse, all ofthe following information bits preferably being present when data istransmitted: group, which is the section or chapter including apredetermined number, such as 1,000 of pages and is the most significantbit of the page address, page which represents one frame in a group, androw which occupies one character space which is preferably 7 bits anddefines a portion of the page preferably containing approximately 11 to13 scan lines which comprise one displayable character. The region Balso preferably contains direct address information, which is the firsttransmitted bit preferably and is a zero unless a direct addresscondition exists which is control condition for a selected terminalinforming the terminal to supercede the requested page. This region Balso preferably contains permission information which is one bitposition which is preferably a one only when the user is being givenauthority to receive one or more selected groups of information. Itshould be noted that preferably there is also an emergency overridecondition which provides control information to all terminals tooverride all requests including the permission request and preferablyoccurs on a page and group information bit location of zero, thiscondition preferably being utilized to display emergency informationsuch as a civil defense warning. Region C is preferably a specialcharacter information region of 7 bits which is preferably utilized foroptional functions to be performed by the individual receiver 28 orterminal. Region D preferably contains 32 characters of displayableinformation in digital form. Region E preferably contains error checkinformation, as will be described in greater detail hereinafter. RegionG is preferably the same as region A and represents the horizontal syncsignal. As was previously mentioned, the vertical sync is preferablyprovided by generating a special sequence of horizontal sync pulsesduring the normal television blanking period, which is afterapproximately 236 horizontal sync pulses, which in the present inventionas in U.S. Pat. No. 3,889,054 is after approximately 15 pages have beentransmitted. Therefore, 15 pages are transmitted before each verticalsync. The sync signal looks like a conventional composite sync signalwith a vertical sync interval comprising approximately nine normalhorizontal sync pulse times as illustrated in FIG. 3 which is anillustration of conventional composite sync and vertical drive signals.

Now referring to FIGS. 4, 20 21A through C, 22 and 23, the improvedvideo processor portion of the receiver 28 of the present inventionshall be described hereinafter. Referring initially to FIG. 20, thecomposite video input signal via path 402 (FIG. 5) is provided to thevideo processor 4000 via path 100 which is the video processor inputtherefor. This signal is conventionally amplified, such as by aconventional transistor amplifier 101 which drives both a conventionalsync separator circuit 102 for providing the vertical sync andhorizontal sync outputs therefrom in conventional fashion, and a videoprocessing circuit 103 to be described in greater detail hereinafter.Video processing circuit 103 preferably extracts the correct logic datafrom the input data from the composite video input signal. This inputdata may contain significant distortions resulting from a conventionalvestigal sideband modulation scheme utilized for transmission as well asfrom phase delay distortion in a cable transmission system and thebandwidth limitations inherent in the FCC channel allocations. Thesedistortions generally occur in any television transmission and are notnormally compensated for due to the low level fidelity requirements ofconventional television transmission and display. The nature of theaforementioned distortion is illustrated in FIGS. 21 A through 21 C.FIG. 21 A represents the original undistorted transmission; FIG. 21 Brepresents the received signal which is provided to a distortioncompensation circuit 111, to be described in greater detail hereinafter,which is preferably included in the video processing circuit 103, thissignal containing distortions as previously mentioned, and FIG. 21 Cillustrates the corrected or distortion compensated signal output fromdistortion compensation circuit 111. The nature of the distortion asillustrated in FIGS. 21 A through 21 C is such that zeros and ones donot always return to the same level, the level of each zero and onebeing dependent on the proceeding few bits of data as illustrated inFIG. 21 B. It should be noted at this point that although the amplitudesof the signals in FIGS. 21 A and 21 C are different, if desired theseamplitudes could be the same, the primary difference between theoriginal undistorted transmission and the corrected signal output ofdistortion compensator 111 being the sloping sides of the pulses presentin the compensated or corrected signal of FIG. 21 C.

The received signal illustrated in FIG. 21 B which contains theaforementioned distortions is preferably provided to the videoprocessing circuit 103 via path 105 which provides this signal to aconventional synchronous clamp circuit 104. As shown and preferred inFIG. 20, this received signal provided via path 105 to synchronous clamp104 is shorted through a reference voltage at a point A at the beginningof each horizontal scan line. This is preferably accomplished by fieldeffect transistor 106 which acts as a fast switch. A gate pulse providedvia path 107 (FIG. 22) which is termed the "keyed clamp gate" signal,turns field effect transistor 106 on through transistor driver 108 for ashort part of the back porch of the signal, this interval being definedas after the color burst which is in region H and before the start bitwhich is the pulse in region J (FIG. 2). As a result, the DC level ofthe data line, represented by path 109, is the same at the start of eachhorizontal scan line. Without the presence of this synchronous clamp104, the DC level would change from line to line depending on therelative number of ones and zeros defining the data content of eachline. Synchronous clamp 104 insures that the receiver terminal 28 willrespond properly to the first data line that follows a group of empty orno data lines. The output of synchronous clamp 104 via data line 109 ispreferably provided to distortion compensation circuit 111 through aconventional isolation amplifier 110 whose input is the data line 109,with isolation amplifier 110 preferably having a high input impedancewhich prevents any average change of DC level during a horizontal scanline period. As illustrated in FIG. 21 B, when distortion is present inthe received signal, there is a significant peak-to-peak change althoughthe value of the location of the peaks may differ. Distortioncompensation circuit 111 preferably responds to the one-to-zero orzero-to-one transitions in the signal. When the transition is azero-to-one transition, as shown and preferred in FIG. 20, the rightside or output side of capacitor 112 rises positively tracking thetransition up to a predetermined voltage, such as preferably the normalthreshold voltage of the silicon diodes 113 and 114 utilized in thedistortion compensation circuit 111, this voltage preferably being byway of example 0.7 volts. At that time, this diode 113, which aspreviously mentioned is preferably a silicon diode, conducts clampingthe voltage at this predetermined value of 0.7 volts even though theinput data may containue to rise in voltage value. This predeterminedvoltage is maintained until a one-to-zero transition occurs. As soon asthe input voltage reverses direction, as caused by a one-to-zerotransition, silicon diode 113 cuts off and the voltage at the right sideor output side of capacitor 112 falls tracking the input change until,preferably, it reaches the negative equivalent of this predeterminedpreferred voltage which, in the example given, is -0.7 volts. At thattime silicon diode 114 which preferably has the same threshold level assilicon diode 113, conducts clamping the voltage at this predeterminedlevel, which by way of example is -0.7 volts, until a zero-to-onetransition occurs at which point silicon diode 114 cuts off and theaforementioned cycle repeats. In this manner a signal is produced whichhas all ones and all zeros of the same respective levels as illustratedin FIG. 21 C. For a string of unchanged ones or unchanged zeros, that iswhere no transition occurs, the clamped voltage output due to silicondiodes 113 and 114 which is provided to the gate of output field effecttransistor 116 of distortion compensation circuit 111 would normallytend to decay as a result of capacitor 112 discharging. In order tocompensate for this, an RC network 115 is connected in parallel acrossthe capacitor 112-diode 113-114 network to provide a reverse tilt orcompensating charge voltage to this decaying voltage to the gate offield effect transistor 116 in order to compensate for the decay. Thisfield effect transistor 116 buffers the clamped output signal andsupplies it to a conventional output amplifier 117 whose output is inturn coupled to a conventional logic inverter 118 through a conventionalbiasing network 119 to provide a true digital data signal at the outputof logic inverter 118 which is equivalent to the original transmittedsignal as illustrated in FIG. 21 C, amplifier 117 amplifying theamplitude of the signal illustrated in FIG. 21 C to the amplitude of thesignal level illustrated in FIG. 21 A. Biasing network 119 preferablyinsures that the switching of logic inverter 118 occurs about midway onthe clamped signal transition, the output of logic inverter 118 beingdigital data.

Referring now to FIG. 22, another portion of the video processingcircuit 4000 is shown. Preferably, the digital data output of logicinverter 118 still contains the color burst which was present in regionH of the signal and would normally remain in the transmitted signal if acolor TV receiver was being utilized for the display terminal. However,when a monochromatic digital TV terminal is utilized, the color burstsignal must preferably be omitted or gated out. It should be noted that,if desired, if only monochromatic TV terminals are to be utilized, thenthe color burst may be omitted all together from the transmitted signalalthough preferably color burst is present to allow for color TVdisplay. The color burst removal circuit illustrated in FIG. 22, asshown and preferred, includes a conventional separatorD-type-divide-by-2 flip-flop 120 which preferably receives a 5.1megahertz clock at the clock input and is preferably cleared by thehorizontal sync provided from sync separator circuit 102 via path 102a(FIG. 20). Flip-flop 120 is preferably connected in a toggle mode sothat its output, which is provided via path 121, is a series of 2.55megahertz pulses, in the example given, that start at the completion ofthe horizontal sync pulse. A conventional decade counter 122 ispreferably connected so as to receive these pulses and count thesepulses so as to generate an output at the tenth pulse which output isprovided via path 123, inverted and then provided through anotherconventional flip-flop 124 which is initially set by the horizontal syncpulse provided via path 102a and reset by the output signal provided vialine 123. The output of flip-flop 124 is preferably a pulse which startswith the beginning of the horizontal sync pulse and ends at thecompletion of the count of the tenth clock pulse as indicated by thepresence of a signal via path 123. The width of this pulse output offlip-flop 124 is preferably such so as to continue beyond the colorburst present in region H but to end prior to the initiation of thestart bit in region J. This pulse clears a conventional flip-flop 124and whose clock input is preferably clocked by the data input providedfrom logic inverter 118 via path 118a (FIG. 20). As a result, the outputof flip-flop 125 which is provided via path 126 is preferably low duringthe horizontal sync and color burst periods and is clocked high by thestart bit of region J contained in the logic inverter 118 outputprovided via path 118a. The signal which is present on path 126 enablesa conventional NAND gate 127 which has two inputs, with the other inputbeing connected to the output of logic inverter 118 via path 118a. As aresult, the output of NAND gate 127 is gated .[.date.]. .Iadd.data.Iaddend.which includes the start bit and subsequent data, such aspresent in regions B through K, but excludes the color burst. A secondconventional two input NAND gate preferably receives the horizontal syncsignal provided via path 102a as one input and the inverted gate signalfrom flip-flop 125 as its other input. As a result, NAND gate 128preferably generates a pulse which starts at the trailing edge of thehorizontal sync signal and terminates with the start bit. This outputsignal from gate 128 is preferably utilized as a delayed horizontal syncsignal for use by other circuits in the receiver terminal 28 as will bedescribed in greater detail hereinafter. It should be noted that thedelayed horizontal sync output of gate 128 which is preferablyterminated with the start bit essentially makes the system insensitiveto any jitter or noise that might be present in the original horizontalsync signal provided via path 102a. As shown and preferred, theaforementioned keyed clamp gate signal provided via path 107 throughvideo processing circuit 103 is preferably provided as the output of athird conventional two input NAND gate 129 whose inputs are thenon-inverted output of flip-flop 124, which is the extended sync signal(FIG. 22 A), and an output from counter 122 which is preferably highafter counting eight pulses as opposed to the tenth pulse count outputprovided via path 123 to flip-flop 124. As a result, the output of gate129 is a pulse that starts eight clock pulses after the end of thehorizontal sync and ends after the tenth clock pulse; in other words,the gate output pulse via path 107 occurs between the eighth and tenthcounts of counter 122. This pulse defines the aforementioned unusedregion on the back porch between the end of the color burst in region Hand the start of the start bit in region J, this area being designatedby reference numeral 11 in FIG. 2.

It should be noted that the aforementioned conventional sync separatorcircuit 102 is preferably identical with that previously described inour U.S. Pat. No. 3,889,054 which description is specificallyincorporated by reference herein.

Referring now to FIG. 4, the improved phase locked loop 4100 (FIG. 5) ofthe preferred synchronization timing portion of the receiver portion 28of the row grabbing system 10 of the present invention is shown, thisphase locked loop 4100 preferably being utilized in place of the phaselocked loop arrangement, described in our previous U.S. Pat. No.3,889,054. Phase locked loop 4100 preferably includes a conventionalvoltage controlled crystal oscillator 130 whose nominal frequency, whichis preferably by way of example 5.1136 megahertz, is set by aconventional crystal 131. This frequency can preferably be varied over asmall range by adjusting the voltage present at input 132. The output ofvoltage controlled oscillator 130 is preferably fed back to aconventional D-type flip-flop 133 at the D input as well as beingprovided via path 401. The gated data output from gate 127 (FIG. 22),which is preferably provided via path 127a, is preferably provided tothe clock input of flip-flop 133 which flip-flop preferably acts as aphase detector. Preferably, whenever a zero-to-one data transitionoccurs while the clock is high, flip-flop 133 is in a set state. If itoccurs when the clock is low, flip-flop 133 is preferably then in thereset state. Thus, a change in the output of flip-flop 133 occurs onlywhen the phasing of the clock changes with respect to the phasing of thedata. It should be noted that preferably the voltage controlledoscillator 130 is the same as the voltage controlled oscillator formingpart of the phase locked loop described in our previous U.S. Pat. No.3,889,054. As shown and preferred, a pair of conventional two input NANDgates 134a and 134b connect the output of the phase detector 133 to theoscillator control circuits only during the valid data period which ispreferably defined as the time of the horizontal scan line including thestart bit when data can be present. One input to gates 134a and 134b,which input is connected in parallel thereto, is the data gate outputfrom flip-flop 25 provided via path 125a (FIG. 22). The other input togate 134a provided via path 135 is the inverted output of flip-flop 133while the other input provided via path 136 to gate 134b is thenon-inverted output of flip-flop 133. If path 135 is high, it denotesthat the clock leads the data in phase whereas if path 136 is high itdenotes that the clock lags the data in phase. When path 136 is high, adiode 137, which is preferably connected to the output of gate 134bthrough an inverter, charges a capacitor 138 connected to the outputthereof in a positive going direction. As long as the phase lagcondition remains, the voltage continues to rise. In the leading phasecondition, that is with path 135 high, this preferably causes capacitor138 to discharge through a diode 139 connected to the output of gate134a. In the normal closed loop condition, the phase varies between avery small leading and very small lagging angle, such as by way ofexample, plus or minus 10°, as necessary to maintain a constant voltageon capacitor 138. This voltage is preferably amplified by a conventionalFET operational amplifier 140, such as an Intersil 8007C, to provide thecontrol voltage for the voltage controlled oscillator 130 via path 132.It should be noted that for the improved phase locked loop 4100, if afull line of data is present, phase locked loop 4100 will utilize everydata transition to continuously correct the clock phase whereas in thecase of a series of empty or non-data lines being transmitted, phaselocked loop 4100 will make a single correction each line utilizing thestart bit which correction will be adequate to insure that phase lockexists at the beginning of the first non-empty or data line. Thus,improved phase lock loop 4100 can maintain phase lock to a single startbit rather than to the entire clock burst as well as utilizing everydata transition to continuously correct clock phase. Thus, phase lockedloop 4100 is an improvement over the phase locked loop arrangementdescribed in our U.S. Pat. No. 3,889,054 which only utilizes the clockburst for phase lock rather than utilizing every data transition. Inorder to prevent large over corrections during periods when lines ae nottransmitted such as when not even the start bit is transmitted, forexample during the vertical blanking interval, during which periods itis important that the last error state at the output of gates 134a and134b does not continue to charge or discharge capacitor 138, such as ifthe last error state was in a leading condition where over correctionwould continue to drive through into a lagging condition, gates 134a and134b are turned off except when an active line, which is defined as aline including a start bit, such as in region J, is received data gatepath 125a. This data gate path 125a preferably goes high coincident withthe start bit and goes low at the beginning of the following horizontalsync pulse so as to indicate the presence of an active line and to thusprevent the occurrence of correction during periods when lines are nottransmitted.

Referring now to FIG. 8, which is a logic diagram, partially inschematic, of a portion of the timing and keyboard control portion ofthe preferred receiver 28 of the present invention illustrated in FIG.5, the circuit shown therein is essentially similar to that describedwith reference to FIG. 8 of our previous U.S. Pat. No. 3,889,054 withthe exception of the improved phase locked loop portion 4100 previouslydescribed with reference to FIG. 4 and with the exception of an improvederror check circuit 432 in place of the error check circuit described inour previous U.S. Pat. No. 3,889,054. As shown and preferred in FIG. 8,the input to error check circuit 432 is preferably resynchronized dataout of flip-flop 760 which, as described in our previous U.S. Pat. No.3,889,054 is an output which preferably follows the input data lineexcept that it will be synchronized with the clock B signal by the clockof flip-flop 760 provided via path 435 which is the same data asutilized by the balance of the receiver display terminal 28. Theresynchronized data preferably goes to the A input of a conventionalsingle bit adder 437 which produces the sum of two input bits present atinputs A and B thereof with the B input initially being zero. This sumis preferably provided via path 439 to the input of a conventional sevenbit shift register 441. The output of shift register 441 is preferablyprovided to the B input of adder 437 through a conventional inverter447. As a result of the seven bit delay provided by register 441, adder437 at any given time adds an input bit of a given character, since thesystem preferably utilizes seven bits per character, with the same bitof the previous character. At the beginning of the line, shift register441 is preferably cleared so that the B input of adder 437 is againlogic zero for the duration of the first character. When the first bitof the second character is received at the A input of adder 437, thefirst bit of the first character is then present at the B input of adder437 and the output of adder 437 provided via path 439 is the sum ofthese two bits. At the beginning of the third character, the B input ofadder 437 represents the sum of bit one from the first two characters.In this manner for the remainder of the line, that is the pseudo videoscan line, the individual bits of the characters are added andaccumulated. This is preferably a serial process which is seriallyrepeated for each of the seven bits of the character; for example, forbit one of character 10, the B input of adder 437 is equivalent to thesum of bits one of characters one through nine and for bit two ofcharacter 10 the B input to adder 437 is equivalent to the sum of bitstwo of charcters one through nine, etc. Adder 437 provides a carryoutput where required by binary addition; namely if one and one areadded, the sum is zero in that position plus a carry of one to the nextposition. This carry output is present on path 451 and is preferablyapplied to the D input of a conventional flip-flop 443 via aconventional two input NAND gate 445. Flip-flop 443 is preferablyclocked by the system clock provided via path 449 so that thenon-inverted output of flip-flop 443 represents the carry output ofadder 437 delayed by one bit. Thus, the carry output present via path451, such as, by way of example, the output that results from theaddition of bit one, is present at the C input of adder 437 when the bittwo addition is taking place. The bit two addition then is a fulladdition resulting from the data bits at A and B of adder 437 as well asthe carry state at C of adder 437. Preferably, a carry output of bitseven is ignored which is accomplished by gate 445 which turns off theinput to flip-flop 443 during bit seven is response to a bit seven pulsefrom the decoder 412 whose operation is described in our previous U.S.Pat. No. 3,889,054, which pulse is provided via path 453. It should benoted that the output of adder 437 via path 439 preferably represents inserial form the accumulated sum of individual character bits.Preferably, during the 38th character, which is preferably the errorcheck character, the accumulated sums will all be ones after the errorcheck character is added in if no error is present. The inverted outputof adder 437 is provided via path 455 to another conventional flip-flop457. Path 455 preferably must be in the zero state during the seven bitsof the 38th character for the received pseudo video scan line to beconsidered a true or valid line. Flip-flop 457 tests for this conditionby being kept in a set state due to a negative preset signal at alltimes except during character 38; in other words, except when the 38thcharacter pulse is provided. Path 455 is connected to the K input of J-Kflip-flop 457 so that if path 455 is high during any bit of the 38thcharacter, flip-flop 457 will be reset. Thus, a negative pulse at thenon-inverted or Q output of flip-flop 457 during the 38th character willindicate an error. Accordingly, the improved error check circuit 432 ofthe present invention adds on a word-by-word basis as opposed to abit-by-bit basis as described in our previous U.S. Pat. No. 3,889,054and accomplishes this summing or addition in serial fashion rather thanparallel fashion.

MICROPROCESSOR AND KEYBOARD SYSTEM

Referring now to FIGS. 24, 26, 27 and 28, the improved microprocessorand keyboard control system of the present invention which preferablyreplaces the keyboard circuitry of the system described in our previousU.S. Pat. No. 3,889,054 will be described. If desired, however, theimproved row grabbing systems of the present invention may continue tooperate with the keyboard circuit arrangement described in our previousU.S. Pat. No. 3,889,054 as opposed to utilizing the improvedmicroprocessor-keyboard control system to be described hereinafterwithout departing from the spirit and scope of the present invention inwhich instance the improved system 10 will contain whichever advantagesdescribed herein are not dependent on the microprocessor-keyboardcontrol system to be described hereinafter. As shown and preferred inFIGS. 27 and 28, the microprocessor 6000 of the present inventionpreferably includes a conventional microcomputer or CPU 601, aconventional read only memory or ROM 603, a conventional random accessmemory or RAM 605, and a conventional input/output buffer or I/O 607.Preferably, the microcomputer 601, read only memory 603, random accessmemory 605 and input/output buffer 607 are all integrated circuit chipsof the type manufactured by Rockwell International, such as what iscommonly available from Rockwell International as their PPS-4 MP systemwherein the microcomputer chip 601 is a Rockwell International 10660CPU, read only memory 603 and random access memory 605 are RockwellInternational 10432 memory chips and input/output buffer chip 607 is aRockwell International 10969. The programming language for thepermanently storable loader and executive program which is preferablystored in read only memory 603 is preferably written in PPS-4 Assemblerlanguage provided from Rockwell International and a typical suchconventional preferred control program for operating the microprocessor6000 of the present invention in accordance with the desired rowgrabbing function for the video display terminal is set forth below,with this version of the program utilizing the arrangement of FIG. 28comprising one CPU chip 601, one 256-by-4 bit random access memory chip605, one 1024-by-8 read only memory chip 603 and two input/output bufferchips 607:

    ______________________________________                                        MICROPROCESSOR 6000 CONTROL PROGRAM                                           ______________________________________                                        *INITIALIZATION                                                               *                                                                             0000 81      T       #1                                                       *SET O/P TO ZERO                                                              0001 7F      LDI     0                                                        0002 10 0E   IOL     #E                                                       0004 7F      LDI     0                                                        0005 10 0D   IOL     #D                                                       0007 7F      LDI                                                              0008 10 07   IOL     1                                                        *RESET FLIP-FLOPS                                                             000A 26      RF1                                                              000B 25      RF2                                                              *CLEAR RAM                                                                    000C 00 00       LBL     D15R15                                               000E 7F IN10     LDI     0                                                    000F 2F          EXD                                                          0010 9E          T       IN10                                                 0011 18          XBHX                                                         0012 1A          XAX                                                          0013 60          ADI     F                                                    0014 98          T       IN20                                                 0015 1A          XAX                                                          0016 18          XBMX                                                         0017 8E          T       IN10                                                 *SET RAM SPECIAL VALUES                                                       0018 0B IN20     LB      R0D9                                                 0019 71          LDI     E                                                    001A 2B          EXD     4      KBD CHARACTER                                                                 (FOR INITIAL                                                                  CALL)                                         001B 7B          LDI     4                                                    0010 2F          EXD     *      CONSTANT (PCC                                                                 BIT MASK)                                     001D 07          LB      R4D5                                                 001E 7E          LDI     1                                                    001F 2F          EXD     *      SEARCHING FOR                                                                 ROW (NOT)                                     0020 02          LB      R6D2                                                 0021 70          LDI     F                                                    0022 3A          EX      5      KBD ROUTINE                                                                   ADDRESS                                       0023 7E          LDI     1                                                    0024 2A          EXD     5      KBD * (INITIAL                                                                LY PAGE 1)                                    0025 70          LDI     F                                                    0026 2F          EXD                                                          0027 7B          LDI     0                                                    0028 3F          EX                                                           0029 50 40       TL      SCHED                                                        *                                                                             *                                                                                      ORG     40                                                   *                                                                             *                                                                             *                                                                             *SCHEDULER                                                                    *CHECKS                                                                       *          (1)RAR CHANGED WITH REN HIGH                                       *            & SCH/RAW CHANGED (PROCESS                                       *            SCH)                                                             *          (2)AS (1) WITH NO SCH/RAW CHANGE                                   *            & RAR APPROACHING PRINT ROW                                      *            (PROCESS RAR)                                                    *          (3) PCC CHANGED & HIGH & PRINT-                                    *            ING IN PROGRESS                                                  *            (PROCESS PRINT)                                                  *          (4)LBD HELD FOR 1 MILLISEC AT                                      *            LEAST (PRECESS KBD)                                              *                                                                             *                                                                             *                                                                             *SCH HAS HIGHEST PRIORITY FOR CHECK                                           *ING CHANGES 110 MICROSEC (22 CYCLES)                                         *BEFORE RAR CHANGES & IS LATCHED UN-                                          *TIL NEW ONE AVAILABLE. RAW DENOTES                                           *ROW TO WHICH IT APPLIES. IF UNCHANGED                                        *SCH FOR THIS RAW EITHER NOT CHANGED                                          *OR REPEATED - IN BOTH CASES                                                  *IGNORE TO AVIOD MULTIPLE                                                     *PRINTS, ETC. CHECKED ONLY WHEN                                               *RAR CHANGES. RAR CHANGES EVERY                                               *13*63 MICROSECS (163 CYCLES), SO HAVE                                        *COMPLETE PROGRAM CYCLE LESS THAN 141                                         *CYCLES IF RAR UNCHANGED LAST TIME.                                           *OR 163 CYCLES IF RAR CHANGED LAST                                            *TIME. RAR ONLY VALID WHEN REN HIGH.                                          *                                                                             *CHECK RAR CHANGED                                                            0040 CD SCHED    LB      R8D10                                                0041 10 19       IOL     #19    GEG RAR                                       0043 00          EOR                                                          0044 1E          SKZ                                                          0045 88          T       *+3    RAR CHANGED                                   0046 50 80                                                                            PCXX     TL      PCCX   RAR UNCHANGED                                 0048 1C 13       1OL     #13    GET REN                                       004A 67          ADI     8                                                    004B 80          T       SCHED  REN GONE LOW                                  004C 1C 19       IOL     #19    REREAD RAR IN                                                                 CASE REN LOW                                                                  WHEN 1ST READ                                 004E 1B          LXA     *      SAVE IN X                                     004F 3F          EX      *      SAVE IN RAM                                   *CHECK SCH/RAW CHANGED                                                        0050 CO          LB      R1                                                   0051 1C 03       IOL     #3     GET RAW                                       0053 19          XABL    *      SET UP SCH TABLE                                                              OFFSET                                        0054 1C 0A       IOL     #A     GET SCH BITS 0-3                              0056 0C          EOR                                                          0057 1E          SHZ                                                          0058 A0          T       SCXX   SCH CHANGED                                   0059 34          LD      3                                                    005A 1C 1A       IOL     #1A    GET SCH BITS 4-6                              005C 0C          EOR                                                          005D 1E          SHZ                                                          005E A5          T       SCYX   SCH CHANGED                                   005F A9          T       RARX   SCH UNCHANGED                                 006Q 0C SCXX     EOR     *      SAVE SCH BITS 0-3                             0061 3C          EX      3                                                    0062 1C 1A       IOL     #1A                                                  0064 0C          EOR                                                          0065 0C SCYX     EOR     *      SAVE SCH BITS 4-6                             0066 9C          EX      3                                                    0067 DF          TM      SCHX   PROCESS SCH                                   0068 80          T       SCHED                                                *                                                                             *                                                                             *IF NO SCH TO BE PROCESSED, NEXT PRIOR-                                       *ITY IS TO SEARCH FOR ROW TO PRINT. IF                                        *THERE IS ONE, THE PRINTER INTERFACE                                          *MUST BE INFORMED WITHIN 189 MICROSECS                                        *(37 CYCLES) OF RAR CHANGING TO CORRECT                                       *VALUE BY PWR PULSE. SO IF RAR IS ONE                                         *BEFORE REQUIRED ROW, SET UP DATA FOR                                         *PRINT & WAIT IN LOOP FOR ROW TO                                              *CHANGE. MAY ALSO BE SEARCHING FOR                                            *ROW NOT TO BE PRINTED. IN THIS CASE,                                         *SEE IF ALL ROWS PRINTED & IF NOT,                                            *START SEARCH FOR NEXT ROW.                                                   *                                                                             *CHECK CORRECT RAR                                                            0069 07 RARX     LB      R4D5                                                 006A 30          LD      7                                                    006B 1E          SHZ                                                          006C 86          T       PCXX   NOT SEARCHING                                                                 FOR ROW                                       006D 12          LAX     *      GET RAR                                       006E 0E          COMP                                                         006F 0B          AD                                                           0070 1E          SHZ                                                          0071 86          T       PCXX   WRONG ROW                                     0072 31          LD      6                                                    0073 19          XABL                                                         0074 37          LD                                                           0075 09          ADSI                                                         0076 B9          T       RWGX   ROW NOT TO BE                                                                 PRINTED                                       0077 53 17       TL      ROWP   PRINT THIS ROW                                0079 53 3D                                                                            RWGX     TL      ROWG   GET NEXT ROW                                  *                                                                             *                                                                             *IF RAR UNCHANGED, NEXT PRIORITY IS TO                                        *CHECK PRINTER CLOCK PCC IS HIGH FOR 27                                       *MSEC (5400 CYCLES) AND ANY PRINT PULSE                                       *MUST BE GIVEN DURING THIS TIME. TO                                           *CATCH THIS HIGH EVERY TIME, MAXIMUM                                          *PROGRAM CYCLE FOR RAR CHANGING MUST                                          *BE 158 CYCLES. IF PRINTING IS IN PRO-                                        *GRESS, ONE OF THE FOLLOWING PULSES                                           *WILL BE GIVEN WHEN PCC CHANGES TO                                            *HIGH:                                                                        *SPA - 16 LEADING SPACES ON 32-CHAR ROW                                       *PRT - PRINT ROW                                                              *BLANK - NO PULSE WHILE WAITING FOR                                           *ROW TO BE PRINTED (32/64 CLOCKS) OR                                          *FOR 1 CLOCK DELAY IN 64-CHAR ROW                                             *WHILE PRINTER I/F READS ROW                                                  *LFD - LINE FEED AFTER ROW & BEFORE                                           *CERTAIN ROWS                                                                 *CAR - CARRIAGE RETURN (AS LFD)                                               *                                                                             *CHECK PCC CHANGED                                                                             ORG     80                                                   0080 CA PCCX     LB      R4D8                                                 0081 1C 13       IOL     #13    GET NEW PCC                                   0083 0D          AND     *      GET BIT 2                                     0084 3F          EX                                                           0085 38          EX      7      (RESTORE CONSTANT)                            0086 3F          EX      *      SAVE NEW PCC                                  0087 0C          EOR     *      BIT 2 = 1 IF                                                                  CHANGED                                       0088 63          ADI     C      CARRY IF                                                                      BIT 2 = 1                                     0089 BC          I       IBXX   PCC, NOT                                                                      CHANGED                                       008A 37          LD                                                           008B 60          ADI     F                                                    008C BD          T       SHDX   NEW PCC = 0                                   008D 1F          DECB                                                         008E 27          LD                                                           008F 60          ADI     F                                                    0080 BD          T       SHDX   PRINTING NOT IN                                                               PROGRESS                                      *SET UP NEXT PRINTER PULSE                                                    0091 1F          DECB                                                         0092 27          LD                                                           0093 60          ADI     F                                                    0094 9F          T       PR30   4-BIT COUNT = 0                               0095 3F          EX      *      STORE COUNT-1                                 0096 17 PR10     INCB                                                         0097 B0          LD      7      GET NEXT O/P                                  0098 0D          AND     *      MASK                                          0099 10 0E                                                                            PR20     IOL     #E     PULSE PRINTER                                 009B 7F          LDI     0                                                    009C 1C 0E       IOL     #E                                                   009E BD          T       SHDX   CONTINUE                                      009F B8 PR30     EX      7      STORE 4-BIT                                                                   COUNT - 1                                     00A0 37          LD                                                           00A1 60          ADI     F                                                    00A2 05          T       PR40   6-BIT COUNT = 0                               00A3 28          EX      7      STORE 6-BIT                                                                   COUNT - 1                                     00A4 96          T       PR10   & O/P NORMALLY                                *GET NEW PRINTER PULSE                                                        00A5 C9 PR40     LB      R3D7                                                 00A6 30          LD      7                                                    00A7 61          ADI     E                                                    00AS AC          T       PR50   NEXT O/P = 1                                                                  (ROW TO BE                                                                    PRINTED NEXT)                                 00A9 C8          LB      R3D6                                                 00AA 7F          LDI     0      CLEAR COUNT FOR                                                               NOW-ROW PRINT                                 00AB B1          T       PR60                                                 00AC 37 PR50     LD      *      GET MASK (=0 FOR                                                              64-CHAR ROW)                                  00AD 2F          EXD     *      (=1 FOR 32-CHAR                                                               ROW)                                          00AE 1E          SKZ                                                          00AF B1          T       PR60   32-CHAR ROW                                                                   (ACC=CT=1)                                    00B0 7C          LDI     3      SET CT FOR 64-                                                                CHAR ROW                                      00B1 BF PR60     EX      *      STORE NEW COUNT                               00B2 C0          LB      R3D7   SHIFT LEFT                                                                    NEXT O/P                                      00B3 37          LD      *      (GET NEW O/P)                                 00B4 0B          AD                                                           00B5 BF          EX                                                           00B6 B7          LD                                                           00B7 1E          SHZ     *      (SKIP IF PRINT                                                                CYCLE COMPLETE)                               00B8 99          T       PR20   PRINT NEW CHAR                                00B9 07          LB      R4D5                                                 00BA 3F          EX      *      SET SEARCHING                                                                 FOR ROW                                       00BB BD          T       SHDX   CONTINUE                                      *                                                                             *                                                                             *IF RAR & PCC UNCHANGED, KBD FUNC-                                            *TIONS ARE ALLOWED. MAXIMUM LENGTH                                            *IN ANY PROGRAM IS LIMITED NUMBER OF                                          *CYCLES, SO A SUSPEND SUBROUTINE IS                                           *USED TO ENTER THE CURRENT PROGRAM,                                           *AND SUSPEND IT WHEN ITS TIME IS UP.                                          *THIS ALLOWS A PART ROUTINE BETWEEN                                           *TWO TM STORE'S *TO BE 63 CYCLES,                                             *OR A COMPLETE *ROUTINE TO BE 25                                              *CYCLES LONG.                                                                 *                                                                             *DO KEYBOARD FUNCTIONS                                                        00BC D1 KBXX     TM      STORE  ENTER CURRENT                                                                 PROGRAM                                       00BD 50 40                                                                            SHDX     TL      SCHED  CONTINUE                                              *                                                                             *                                                                                      ORG     300                                                  *INITIAL 1 BD PROGRAM                                                         0300 CC KBYX     LB      R3D9                                                 0301 70          LDI     F                                                    0302 09          ADSK                                                         0303 8E          T       1 BX20 KBD CT. = 0                                   0304 3C          EX      3      SAVE CT. -1                                   0305 10 09       IOL     #9     GET KBD                                       0307 0C          EOR                                                          0308 1E          SKZ                                                          0309 8B          T       1 BX10 KBD CHANGED                                   030A 95          T       1 BX40 KBD UNCHANGED                                 030B 00 1 BX10   EOR                                                          030C 3C          EX      3      STORE NEW KBD                                 030D 9B          T       1 BX30                                               *ENTER 1 BD RECORDER                                                          030E B4 1 BX20   LD      3                                                    030F DB          TM      1 BDX  ENTER KBD                                                                     ROUTINE                                       0310 7D 1 BX25   LDI     2                                                    0311 DB          TM      PLSB   PULSE KBR                                     0312 00          LB      R3D9                                                 0313 7B 1 BX30   LDI     4      RESET COUNT                                   0314 BF          EX                                                           0315 D1 1 BX40   TM      STORE  SUSPEND - RETURN                                                              TO SECHEDULER                                 0316 80          T       KBYX                                                 *                                                                             *                                                                             *RAR PROCESSING - SET UP DATA FOR                                             *PRINT & WAIT FOR RAR TO CHANGE.                                              *                                                                             0317 7F ROWP     LDI     0                                                    0318 3B          EX      4      CLEAR PRINT BIT                               0319 37          LD      *      GET SCH FOR ROW                               031A 09          ADSK    *      0 SET & SKIP IF 64-                                                           CHAR ROW                                      031B 71          LDI     E      32-CHAR ROW                                   031C 70          LDI     F      64-CHAR ROW                                   031D 1C 1D       IOL     #1D    SET RWL                                       031F 0E          COMP                                                         0320 00 B8       LBL D7R4                                                     0322 38          EX      7      SAVE MASK                                     0323 7E          LDI     1                                                    0324 28          EXD     7      SET NEXT O/P TO                                                               SPACE                                         0325 15          SKC                                                          0326 AB          T       RP10   32-CHAR ROW                                   0327 38          EX      7      SET CT. FOR 64-                                                               CHAR. ROW                                     0328 7E          LDI     1      (DELAY CT. = 1)                               0329 28          EXD     7                                                    032A AD          T       RP20                                                 032B 7E RP10     LDI     1      SET CT. FOR 32-CHAR.                                                          ROW                                           032C 2F          EXD     *      (SPACE CT. = 16)                              032D 7E RP20     LDI     1                                                    032E 3D          EX      2      CLEAR SEARCHING                                                               FOR ROW                                       032F 3A          EX      5      CLEAR ROW                                                                     COUNT                                         0330 1C 19                                                                            RP30     IOL     #19    WAIT FOR RAR TO                                                               CHANGE                                        0332 0C          EOR                                                          0333 1E          SKZ                                                          0334 B0          T       RP30   WRONG RAR                                     0335 1C 13       IOL     #13                                                  0337 67          ADI     8                                                    0338 B0          T       RP30   REN LO                                        0339 7E          LDI     1                                                    033A D3          TM      PLSB   PULSE PWR                                     033B 50 40                                                                            RF40     TL      SCHED  CONTINUE                                      *                                                                             *                                                                             *RAR PROCESSING - GET NEXT ROW                                                *                                                                             033D D7 ROWO     TM      GETROW                                               003E BB          T       RP40   CONTINUE                                              *                                                                             *                                                                             *                                                                                      ORG     CO                                                           *                                                                     *PAGE 3                                                                       *DATA ADDRESSES                                                               *SUBROUTINE ADDRESSES                                                         *EQUATES                                                                      *                                                                             *EQUATES                                                                      DOR0         EQU     00       GROUP # 3RD                                                                   DIGIT                                           DOR3         EQU     30       KBD # MOST SIG.                                                               DIGIT                                           D2R4         EQU     42       WORKSPACE (FOR                                                                BINARY*2)                                       D5R4         EQU     45       SEARCHING FOR                                                                 ROW (WHEN ZERO)                                 D5R6         EQU     65       ROW COUNT                                       D7R3         EQU     37       NEXT O/P                                        D7R4         EQU     47       MASK                                            D15R2        EQU     2F       TOP OF SCH TABLE                                D15R5        EQU     5F       TOP OF ROW STAT-                                                              US REGISTER                                     D15R15       EQU     FF       TOP OF USED RAM                                 *DATA ADDRESSES                                                               00C0 EF R1       TR      #10    SCH TABLE                                     00C1 FD R0D2     PTR     #02    GROUP #                                       00C2 9D R6D2     PTR     #62    SAVED KBD                                                                     ROUTINE ADDRESS                               00C3 8D R7D2     PTR     #72    PAGE NUMBER                                   00C4 CD R3D2     PTR     #32    CURRENT KBD                                                                   NUMBER                                        00C5 8C R7D3     PTR     #73    INITIALISING                                  00C6 CA R3D5     PTR     #35    CURRENT ROW                                   00C7 BA R4D5     PTR     #45    SEARCHING FOR                                                                 ROW (WHEN ZERO)                               00C8 C9 R3D6     PTR     #36    PRINT COUNT                                   00C9 C8 R3D7     PTR     #37    NEXT O/P                                      00CA B7 R4D8     PTR     #48    MASK FOR PCC                                                                  VALUE                                         00CB F6 R0D9     PTR     #09    KEYBOARD                                                                      CHARACTER                                     00CC C6 R3D9     PTR     #39    KEYBOARD COUNT                                00CD C6 R3D10    PTR     #3A    LAST RAR                                      00CE FF          PTR                                                          00CF FF          PTR                                                          *SUBROUTINE ADDRESSES                                                         00D0 FD INDEX    PTR     ZINDE  SWITCH ROUTINE                                00D1 E2 STORE    PTR     ZSTOR  SUSPEND OR RE-                                                                ENTER KBD                                                                     ROUTINE                                       00D2 F6 SHIFT    PTR     ZSHIF  DOUBLE BINARY                                                                 NUMBER                                        00D3 E8 PLSB     PTR     ZPLSB  SET AC AS PULSE                                                               ON I/O 0 GRP B                                00D4 6C CLEAR    PTR     ZCLEA  CLEAR 3 DIGITS                                00D5 65 SCHRS    PTR     ZSCHR  RESET SPECIAL                                                                 CHARACTERS                                    00D6 EF PEND     PTR     ZPEND  STOP PRINTING &                                                               MODE A                                        00D7 BF                                                                              GETROW    PTR     ZGETR  GET NEXT ROW                                  00D8 D6 1 BDX    PTR     ZKBDX  SELECT KBD                                                                    ROUTINE                                       00D9 8F NUM      PTR     ZNUM   KBD ROUTINES                                                                  (IF <26 CYCLES,                                                               BEGIN XS,                                     00DA 5D GRP      PTR     ZGRP   FINISH RTN, IF                                                                >25 CYCLES, DO                                00DB 07 PRINT    PTR     ZPRIN  NOT BEGIN XS,                                                                 FINISH TL KBX25,                                                              BREAK UP                                      00DC 38 UP       PTR     ZUP    INTO 63 CYCLE                                                                 BLOCKS)                                       00DD 1C BACK     PTR     ZBACK                                                00DE 5D CALL     PTR     ZGRP                                                 00DF FF SCHX     PTR     ZSCHX  JUMP TO SCH                                                                   DECORDER                                      00E0 74 ERASE    PTR     ZERAS  SCH ROUTINES                                                                  (BEGIN ALL                                                                    WITH XS)                                      00E1 9C PROWO    PTR     ZPROW  (FINISH RTN)                                  00E2 99 PROWX    PTR     ZPROX  (MUST BE <114                                                                 CYCLES)                                       00E3 70 ERAS2    PTR     ZERA2  ERASE SCREEN                                                                  (BY KBD)                                      00E4 7F PGPRT    PTR     ZPP20  PAGE PRINT                                                                    (BY KBD)                                      00E5 94 RWPRT    PTR     ZPX15  ROW PRINT                                                                     (BY KBD)                                              *                                                                             *                                                                             *                                                                                      ORG     100                                                          *                                                                     *PAGES 4-7                                                                    *SUBROUTINES CALLED BY TM                                                     *                                                                             *                                                                             *GO TO SKR FOR SCH PROCESSING                                                 0100 52 2F                                                                            ZSCHX    TL      SCHY                                                         *                                                                             *                                                                             *                                                                     *INDEX - SWITCH ROUTINE                                                       *SETS RETURN ADDR BITS 0-3 TO COMP. OF                                        *M & ADDS COMP. OF M EOR 3 TO RETURN                                          *ADDR. BITS 4-7 LEAVES B AS B EOR 3                                           *SWITCH TABLE MUST START AT 16-WD.                                            *BLOCK & LIE WITHIN 256-WD. BLOCK.                                            *CALLING INSTRUCTION MUST BE AT                                               *16-WD BOUNDRY - 1.IF M EOR 3 = 0 IS NOT                                      *TO AFFECT BITS 4-7 OF RETURN ADDRESS,                                        *TABLE MUST NOT START AT 64-WD. BLOCK &                                       *CALLING INSTRUCTION MUST                                                     *IMMEDIATELY PRECEDE IT. IF                                                   *M EOR 3 = -1 IS NOT TO AFFECT BITS 4-7                                       *OF RETURN ADDRESS, CALLING                                                   *CALLING INSTRUCTION MUST BE 17                                               *WORDS BEFORE TABLE & NOT AT END                                              *OF 64-WORD BLOCK.                                                            0102 6F ZINDE    CYS                                                          0103 34          LD      3                                                    0104 6F          CYS                                                          0105 0B          AD                                                           0106 6F          CYS                                                          0107 6F          CYS                                                          0108 05          RTN                                                          *                                                                             *                                                                             *                                                                             *MULTIPLY BINARY # BY 2                                                       *BY ADDING TO ITSELF                                                          *                                                                             0109 C3 ZSHIF    LB      R7D2                                                 010A 24          RC                                                           010B 37 ZS10     LD                                                           010C 0A          ADC                                                          010D 2F          EXD                                                          010E 8B          T       XS10                                                 010F 05          RTN                                                          *                                                                             *                                                                             *                                                                             *STOP PRINTING                                                                *CLEAR MODE A                                                                 *CLEAR ALL ROW, CRLF BITS                                                     *                                                                             0110 26 ZPEND    RF1     *      CLEAR MODE A                                  0111 00 A0       LBL     D15R5                                                0113 7F PE10     LDI     0      CLEAR ROW,                                                                    CRLF BITS                                     0114 2F          EXD                                                          0115 93          T       PE10                                                 0116 05          RTN                                                          *                                                                             *                                                                             *                                                                             *PULSE OUTPUT ROUTINE                                                         *SET O/P ON GROUP B OF I/O 0                                                  *TO ACCUMULATOR & CLEAR                                                       *IMMEDIATELY.                                                                 *PULSE LENGTH = 15 MICROSEC.                                                  0117 1C 0D                                                                            ZPLSB    IOL     #D                                                   0119 7F          LDI     0                                                    011A 10 0D       IOL     #D                                                   0110 05          RTN                                                          *                                                                             *                                                                             *                                                                             *SUSPEND OR RE-ENTER KBD ROUTINE                                              *PROGRAM. MUST NOT BE IN ANY KBD                                              *ROUTINE TOO LONG SO CALLING -*THIS WILL STORE CURRENT ADDRESS &              *RETURN TO THE LAST STORED ADDRESS.                                           *STORED ADDRESS INITIALLY SET TO KBYX                                         *SO CALLED AT KBXX TO ENTER, & AFTER                                          *BLOCKS OF KBD ROUTINE TO SUSPEND.                                            011D C2 ZSTOR    LB      R6D2                                                 011E 6F ST10     CYS                                                          011F 2F          EXD                                                          0120 9E          T       ST10                                                 0121 6F          CYS                                                          0122 05          RTN                                                          *                                                                             *                                                                             *                                                                             *PROCESS KBD                                                                  *POSSIBLE KBD VALUES.                                                         *0-9 NUMERALS                                                                 *10 GROUP                                                                     *11 PRINT                                                                     *12 UP                                                                        *13 BACK                                                                      *14 CALL                                                                      *15 IDLE STATE                                                                                 ORG     129                                                  0129 33 ZKBDX    LD      4      GET KBD CHAR.                                 012A 3B          EX      4      SAVE & GET                                                                    LAST KBD                                      012B 0C          EOR                                                          012C 1E          SKZ     *      NOT CHANGED?                                  012D AF          T       *+2    PROCESS NEW KBD                               012E 05          RTN                                                          *THIS TABLE MUST BEGIN AT END OF 16-WD                                        *BLOCK & LIE WITHIN A 64-WD BLOCK.                                            012F D0      TM      INDEX    (RETURN ADD-                                                                  RESS = P + SWITCH                                                             INDEX)                                          0130 05      RTN     *        NO CHARACTER                                    0131 DE      TM      CALL                                                     0132 DD      TM      BACK                                                     0133 DC      TM      UP                                                       0134 DB      TM      PRINT                                                    0135 DA      TM      GRP                                                      0136 D9      TM      NUM                                                      0137 D9      TM      NUM                                                      0138 D9      TM      NUM                                                      0139 D9      TM      NUM                                                      013A D9      TM      NUM                                                      013B D9      TM      NUM                                                      013C D9      TM      NUM                                                      013D D9      TM      NUM                                                      013E D9      TM      NUM                                                      013F D9      TM      NUM                                                      ***END OF TABLE                                                               *                                                                             *                                                                             *                                                                             *GET NEXT ROW & PRINT LEADING CRLF IF                                         *NECESSARY. STOP PRINT MODE A IF ROW                                          *COUNT = 16 (CLEARED WHENEVER ROW                                             *OR CRLF PRINTING IS SET UP, OR WHEN                                          *A ROW PRINT OR CRLF BIT IS SET IN                                            *ROW STATUS; INCREMENTED EACH TIME                                            *NEXT ROW GOT). CALLED WHEN ROW                                               *PRINTED TO GET NEXT, OR WHEN PRINT-                                          *ING TO BE STARTED (WHEN PUT                                                  *CURRENT ROW = 1ST ROW - 1).                                                  *                                                                             *GET NEXT ROW                                                                 0140 00 BA                                                                            ZGETR    LBL     D4R4                                                 0142 7F          LDI     0                                                    0143 38          EX      7      SET SEARCHING                                                                 FOR ROW                                       0144 7E          LDI 1                                                        0145 0B          AD                                                           0146 3F          EX      *      INCR. CURRENT                                                                 ROW                                           0147 31          LD      6                                                    0148 19          XABL    *      GET ROW STATUS                                0149 7B          LDI     4                                                    014A 0D          AND                                                          014B 1E          SKZ                                                          014C 98          T       GT20   CRLF BIT SET                                  014D 00 9A       LBL     D5R6                                                 014F 37          LD                                                           0150 6E          ADI     1      INCR. ROW COUNT                               0151 96          T       GT10   NOT YET SCANNED                                                               ALL 16 ROWS                                   *TERMINATE KBD PRINT MODE                                                     0152 26          RF1     *      CLEAR PRINT                                                                   MODE A (ALL                                                                   ROWS PRINTED)                                 0153 3D          EX      2                                                    0154 7E GT05     LDI     1                                                    0155 3D          EX      2      CLEAR SEARCH-                                                                 ING FOR ROW                                   0156 3F GT10     EX      *      CLEAR (OR STORE)                                                              ROW COUNT                                     0157 05          RTN                                                          *PRINT LEADING CRLF                                                           0158 0C GT20     EOR                                                          0158 3F          EX      *      CLEAR CRLF BIT                                015A 00 C8       LBL     D7R3                                                 015C 7D          LDI     2                                                    015D 2F          EXD     *      SET TO PRINT                                                                  LFD NEXT                                      015E 7F          LDI     0                                                    015F 38          EX      7      PRINT COUNT = 0                               0160 7F          LDI     0                                                    0161 2F          EXD                                                          0162 94          T       GT05                                                 *                                                                             *                                                                             *                                                                             ****SPECIAL CHARACTER ROUTINES                                                *                                                                             *                                                                             *                                                                             *SPECIAL CHARACTER ROW PRINTS                                                 *PROWX - ONLY IF IN MODE B, NO LEADING                                        *CRLF                                                                         *PROWO - ALWAYS                                                               *                                                                             0163 06 ZPROW    XS      *      DISCARD RETURN                                                                ADDRESS                                       0164 30          LD      7                                                    0165 AB          T       ZPX15                                                0166 06 ZPROX    XS                                                           0167 14          SKF2                                                         0168 05          RTN     *      NOT MODE B                                    0169 30          LD      7                                                    016A 77          LDI     8      SET ONLY ROW                                                                  PRINT BIT                                     016B 73 ZPX15    LDI     C      ENTRY FROM KBD                                                                ROUTINE                                       016C 2F          EXD     *      SET CRLF & ROW                                                                PRINT BITS                                    016D AE          T       *+1    (IGNORE SKIP)                                 016E 11          LABL    *      SAVE ROW-1                                    016F 1B          LXA                                                          0170 00 9A       LBL D5R6                                                     *ENTRY POINT FROM PPGEX                                                       0172 7F PX20     LDI     0                                                    0173 3D          EX      2      CLEAR ROW                                                                     COUNT                                         0174 37          LD                                                           0175 60          ADI     F                                                    0176 05          RTN     *      SEARCHING FOR                                                                 ROW                                           0177 C9          LB      R3D7                                                 0178 37          LD                                                           0179 1E          SKZ                                                          017A 05          RTN     *      PRINTING IN                                                                   PROGRESS                                      017B C6          LB      R3D5                                                 017C 12          LAX                                                          017D 3F          EX      *      SET CURRENT                                                                   ROW                                           017E D7          TM      GETROW PRINT IT                                      017F 05          RTN                                                                  *                                                                             *                                                                                      ORG     180                                                  *                                                                             *                                                                             *SPECIAL CHARACTER PAGE PRINT                                                 *NO LONGER USED FOR SCH                                                       *ONLY USED FOR COMPLETION OF KBD                                              *PAGE PRINT                                                                   *SCH CODE LEFT AS COMMENTS IN CASE OF                                         *FUTURE USE                                                                   *                                                                             *ZPPGE XS * DISCARD RETURN ADDRESS                                            *SKF2                                                                         *RTN * NOT MODE B                                                             *LBL D15R5                                                                    *PP10 LDI 8 SET ROW BIT ON ALL ROWS                                           *EXD                                                                          *T PP10                                                                       0180 17 ZPP20    INCB    *      ENTRY FROM KBD                                                                ROUTINE                                       0181 82          T       *+1                                                  0182 73          LDI     C      SET CRLF BIT ON                                                               ROW 1                                         0183 3F          EX                                                           0184 C6          LB      R3D5                                                 0185 7F          LDI     0                                                    0186 3A          EX      5      CURRENT ROW = 0                               0187 70          LDI     F                                                    0188 1B          LXA     *      SAVE CURRENT                                                                  ROW IF GETROW                                                                 CALLED                                        0189 51 72       TL      PX20                                                 *                                                                             *                                                                             *                                                                             *SPECIAL CHARACTER ERASE                                                      018B 06 ZERAS    XS                                                           018C 7B XERA2    LDI     4      ENTRY FROM KBD                                                                ROUTINE                                       018D D3          TM      PLSB                                                 018E 05          RTN                                                          *KBD S/R - ERASE SCREEN                                                       018F 7D ZERA2    LDI     2                                                    0190 1C 17       IOL     #17    SET KAC                                       0192 8C          T       XERA2  ERASE SCREEN                                  *                                                                             *                                                                             *                                                                             *                                                                             *                                                                             *                                                                             ****EXTRA UTILITIES                                                           *                                                                             *                                                                             *                                                                             *CLEAR 3 SUCCESSIVE RAM DIGITS                                                0193 7F ZCLEA    LDI     0                                                    0194 2F          EXD                                                          0195 7F          LDI     0                                                    0196 2F          EXD                                                          0197 7F          LDI     0                                                    0198 3F          EX                                                           0199 05          RTN                                                          *                                                                             *                                                                             *                                                                             *RESET SPECIAL CHARACTERS                                                     019A 00 D0                                                                            ZSCHR    LBL     D15R2                                                019C 7F SR10     LDI     0                                                    019D 3C          EX      3                                                    019E 7F          LDI     0                                                    019F 2C          EXD     3                                                    01A0 9C          T       SR10                                                 01A1 05          RTN                                                          *                                                                             *                                                                             *                                                                             ****KEYBOARD ROUTINES                                                         *                                                                             *                                                                             *                                                                             *PROCESS GROUP KEY                                                            *NO GROUP IGNORED                                                             *INVALID GROUP SET TO ZERO, WITH                                              *PAGE 10                                                                      *GOOD GROUP # SENT TO TERMINAL WITH                                           *PGE # ZERO                                                                   *                                                                             *                                                                             *PROCESS CALL KEY                                                             *NO NUMBER = 0                                                                *GROUP NUMBER NOT AFFECTED                                                    *NEW PAGE NUNBER SENT TO TERMINAL                                             *                                                                             01A2 E3 ZGRP     TM      ERAS2  CLEAR SCREEN                                  01A3 00 CF       LBL     DOR3                                                 01A5 37          LD                                                           01A6 6E          ADI     1                                                    01A7 AE          T       K10    NUMBER IN-                                                                    SERTED BEFORE                                                                 GROUP/CALL                                    01A8 3F          EX      *      NO NUMBER = 0                                 01A9 CB          LB      R0D9                                                 01AA 37          LD                                                           01AB 6A          ADI     5                                                    01AC 53 D2       TL      RESET  FROM GRP -                                                                    IGNORE NO #                                           *                                                                     01AE D1 K10      TM      STORE  WAIT                                                  *                                                                     01AF 53 40       TL      XGPCL  SELECT NEW                                                                    GROUP/PAGE                                            *                                                                             *                                                                                      ORG     1C0                                                  *                                                                             *                                                                             *PROCESS NUMERAL KEY                                                          *ADD INTO CURRENT 3-DIGIT NUMBER                                              *EXCESS DIGITS SHIFTED OFF END                                                *                                                                             01C0 06 ZNUM     XS                                                           01C1 34          LD      3      GET KBD CHAR-                                                                 ACTER                                         01C2 37          LD                                                           01C3 C4          LB      R3D2                                                 01C4 2F NM10     EXD     *      INSERT IN KBD                                                                 NUMBER                                        01C5 84          T       NM10                                                 01C6 05          RTN                                                          *                                                                             *                                                                             *                                                                             *PROCESS UP KEY                                                               *IGNORED IF PAGE # AT HIGH LIMIT                                              *ELSE INCREMENTS PAGE NUMBER                                                  *                                                                             01C7 E3 ZUP      TM      ERAS2  CLEAR SCREEN                                          *                                                                     01C8 D1          TM      STORE  WAIT                                                  *                                                                     01C9 C3          LB      R7D2                                                 01CA 37          LD                                                           01CB 66          ADI     9                                                    01CC 98          T       UP30   BITS 0-3 NOT 7-F                              01CD 1F          DECB                                                         01CE 37          LD                                                           01CF 6D          ADI     2                                                    01D0 98          T       UP30   BITS 4-7 NOT E/F                              01D1 1F          DECB                                                         01D2 7C          LDI     3                                                    01D3 0D          AND                                                          01D4 62          ADI     D                                                    01D5 98          T       UP30   BITS 8-9 NOT 3                                01D6 53 D2                                                                            UP15     TL      RESET  PAGE NUMBER AT                                                                HIGH LIMIT                                            *                                                                     01D8 D1 UP30     TM      STORE WAIT                                           *UP ACCEPTED                                                                  01D9 C3          LB      R7D2   ADD 1 TO PAGE #                               01DA 24          RC                                                           01DB 7E          LDI     1                                                    01DC 9E          T       UP50                                                 01DD 7F UP40     LDI     0                                                    01DE 0A UP50     ADC                                                          01DF 2F          EXD                                                          01E0 9D          T       UP40                                                 01E1 53 96       TL      SEND   SEND TO                                                                       TERMINAL                                      *                                                                             *                                                                             *                                                                             *PROCESS BACK KEY                                                             *IGNORED IF PAGE # AT ZERO                                                    *ELSE DECREMENTS PAGE NUMBER                                                  *                                                                             01E3 E3 ZBACK    TM      ERAS2  CLEAR SCREEN                                  01E4 C3          LB      R7D2                                                 01E5 37 BK 10    LD                                                           01E6 1E          SKZ                                                          01E7 AF          T       BK20                                                 01E8 1F          DECB                                                         01E9 40          SKBI    0                                                    01EA A5          T       BK10                                                 01EB 73          LDI     C                                                    01EC 0F          OR                                                           O1ED 6C          ADI     3                                                    01EE 96          T       UP15   PAGE NUMBER = 0                                       *                                                                     01EF D1 BK20     TM      STORE  WAIT                                          *BACK ACCEPTED                                                                01F0 C3          LB      R7D2   SUBTRACT 1 FROM                                                               PAGE #                                        01F1 24          RC                                                           01F2 70 BK30     LDI     F                                                    01F3 0A          ADC                                                          01F4 2F          EXD                                                          01F5 B2          T       BK30                                                 01F6 53 9A       TL      SEND   SEND TO                                                                       TERMINAL                                      *                                                                             *                                                                             *                                                                             *PROCESS PRINT KEY                                                            *CODE IN ANOTHER PAGE                                                         *                                                                             01F8 52 C0                                                                            ZPRIN    TL      XPRIN                                                        *                                                                             *                                                                             *                                                                                      ORG     22F                                                  *                                                                             *PAGES 8-15                                                                   *(EXCEPT PAGE 12 300-33F USED ALREADY)                                        *SUBROUTINES CALLED BY TML                                                    *OR OTHER PROGRAMS                                                            *                                                                             *                                                                             *                                                                             *PROCESS SCH                                                                  *THIS TABLE MUST BEGIN AT THE END OF                                          *A 16-WD BLOCK (NOT FA 64-WORK BLOCK)                                         *& LIE WITHIN A 256-WD BLOCK, & THE                                           *SWITCH TABLE MUST BE 16 WORDS ON                                             *FROM CALLING INSTRUCTION                                                     022F D0 SCHY     TM      INDEX  (RETURN ADD-                                                                  RESS =  P + SWITCH                                                            INDEX)                                        *AN SCH 7F WILL ADD 1 TO RETURN ADDR                                          *BITS 4-7 & THEREFORE RETURN HERE                                             *(16 WDS ON FROM CALLING INSTRUCTION)                                         ORG          240                                                              0240 05      RTN                                                              0241 05      RTN                                                              0242 05      RTN                                                              0243 05      RTN                                                              0244 05      RTN                                                              0245 05      RTN                                                              0246 05      RTN                                                              0247 05      RTN                                                              0248 05      RTN                                                              0249 05      RTN                                                              024A 05      RTN                                                              024B 05      RTN                                                              024C 05      RTN                                                              024D 05      RTN                                                              024E 05      RTN                                                              024F 05      RTN                                                              0250 05      RTN                                                              0251 05      RTN                                                              0252 05      RTN                                                              0253 05      RTN                                                              0254 05      RTN                                                              0255 05      RTN                                                              0256 05      RTN                                                              0257 05      RTN                                                              0258 05      RTN                                                              0259 05      RTN                                                              025A 05      RTN                                                              025B 05      RTN                                                              025C 05      RTN                                                              025D 05      RTN                                                              025E 05      RTN                                                              025F 05      RTN                                                              0260 05      RTN                                                              0261 05      RTN                                                              0262 05      RTN                                                              0263 05      RTN                                                              0264 05      RTN                                                              0265 05      RTN                                                              0266 05      RTN                                                              0267 05      RTN                                                              0268 05      RTN                                                              0269 05      RTN                                                              026A 05      RTN                                                              026B 05      RTN                                                              026C 05      RTN                                                              026D 05      RTN                                                              026E 05      RTN                                                              026F 05      RTN                                                              0270 05      RTN                                                              0271 05      RTN                                                              0272 05      RTN                                                              0273 05      RTN                                                              0274 05      RTN                                                              0275 05      RTN                                                              0276 05      RTN                                                              0277 05      RTN                                                              0278 05      RTN                                                              0279 05      RTN                                                              027A 05      RTN                                                              027B 05      RTN                                                              027C 05      RTN                                                              027D 05      RTN                                                              027E 05      RTN                                                              027F 05      RTN                                                              0280 05      RTN                                                              0281 05      RTN                                                              0282 05      RTN                                                              0283 05      RTN                                                              0284 05      RTN                                                              0285 05      RTN                                                              0286 05      RTN                                                              0287 05      RTN                                                              0288 05      RTN                                                              0289 05      RTN                                                              028A 05      RTN                                                              028B 05      RTN                                                              028C 05      RTN                                                              028D 05      RTN                                                              028E 05      RTN                                                              028F 05      RTN                                                              0290 05      RTN                                                              0291 05      RTN                                                              0292 05      RTN                                                              0293 05      RTN                                                              0294 05      RTN                                                              0295 05      RTN                                                              0296 E1      TM      PROWO    SCH=41                                          0297 05      RTN                                                              0298 05      RTN                                                              0299 05      RTN                                                              029A 05      RTN                                                              029B 05      RTN                                                              029C 05      RTN                                                              029D 05      RTN                                                              029E E1      TM      PROWO    SCH=33                                          029F E0      TM      ERASE    SCH=32                                          02A0 E2      TM      PROWX    SCH=31                                          02A1 05      RTN                                                              02A2 E2      TM      PROWX    SCH=29                                          02A3 05      RTN                                                              02A4 E2      TM      PROWX    SCH=27                                          02A5 05      RTN                                                              02A6 E2      TM      PROWX    SCH=25                                          02A7 05      RTN                                                              02A8 E2      TM      PROWX    SCH=23                                          02A9 05      RTN                                                              02AA E2      TM      PROWX    SCH=21                                          02AB 05      RTN                                                              02AC E2      TM      PROWX    SCH=19                                          02AD 05      RTN                                                              02AE E2      TM      PROWX    SCH=17                                          02AF 05      RTN                                                              02B0 E2      TM      PROWX    SCH=15                                          02B1 05      RTN                                                              02B2 E2      TM      PROWX    SCH=13                                          02B3 05      RTN                                                              02B4 E2      TM      PROWX    SCH=11                                          02B5 05      RTN                                                              02B6 E2      TM      PROWX    SCH=9                                           02B7 05      RTN                                                              02B8 E2      TM      PROWX    SCH=7                                           02B9 05      RTN                                                              02BA E2      TM      PROWX    SCH=5                                           02BB 05      RTN                                                              02BC E2      TM      PRWOX    SCH=3                                           02BD 05      RTN                                                              02BE E2      TM      PROWX    SCH=1                                           02BF 05      RTN     *        SCH-0                                           ***END OF TABLE                                                               *                                                                             *                                                                             *                                                                             ****MORE KEYBOARD ROUTINES IN                                                 ****PAGES 8-15                                                                *                                                                                        ORG   2C0                                                          *                                                                             *                                                                             *PROCESS PRINT KEY                                                            *NO NUMBER = PRINT PAGE OR STOP PRINT                                         *NUMBER 0 = START MODE B                                                      *NUMBER 1-16 = PRINT ROW                                                      *                                                                             02C0 00 CF                                                                            XPRIN    LBL     DOR3                                                 02C2 37          LD                                                           02C3 6E          ADI     1                                                    02C4 9A          T       P60    NUMBER INSERTED                                       *                                                                     02C5 D1          TM      STORE  WAIT                                          *NO NUMBER INSERTED                                                           02C6 16          SKF1                                                         02C7 89          T       P10                                                  02C8 8B          T       P20    MODE A                                        02C9 14 P10      SKF2                                                         02CA 8E          T       P30    NOT MODE B                                    *STOP PRINTING                                                                02CB 25 P20      RF2     *      CLEAR MODE B                                  02CC D6          TM      PEND   CLEAR MODE A,                                                                 ROW, CRLF BITS                                02CD 98          T       P50    EXIT                                          *PRINT PAGE                                                                   02CE 22 P30      SF1     *      SET MODE A                                    02CF 00 A0       LBL     D15R5                                                02D1 77 P40      LDI     8      SET ALL ROW BITS                              02D2 2F          EXD                                                          02D3 91          T       P40                                                          *                                                                     02D4 D1          TM      STORE  WAIT                                                  *                                                                     02D5 00 A0       LBL     D15R5  RESET B                                       02D7 E4          TM      PGPRT  USE SCH ROUTINE                                                               TO SET REST OF                                                                DATA                                          02D8 53 D2                                                                            P50      TL      RESET  RESET KBD #                                                                   AND EXIT                                      *NUMBER INSERTED                                                              02DA 04 P60      LB      R3D2                                                 02DB 37          LD                                                           02DC 66          ADI     9                                                    02DD 9F          T       P70                                                  02DE A6          T       P80                                                  02DF    P70      DECB                                                         02E0 7E          LDI     1                                                    02E1 0C          EOR                                                          02E2 1E          SRZ                                                          02E3 B1          T       P90                                                  02E4 17          INCB                                                         02E5 76          LDI     9                                                    02E6 70 P80      LDI     F                                                    02E7 0B          AD                                                           *PRINT ROW                                                                    02E8 22          SF1     *      SET MODE A                                    02E9 25          RF2     *      CLEAR MODE B                                  02EA 3F          EX      *      SAVE ROW *                                            *                                                                     02EB D1          TM      STORE  WAIT                                                  *                                                                     02EC 04          LB      R3D2                                                 02ED 39          EX      6      GET ROW *                                     02EE 19          XABL    *      GET ROW                                                                       STATUS WORD                                   02EF E5          TM      RWPRT  USE SCH ROUTINE                                                               TO SET REST                                                                   OF DATA                                       02F0 98          T       P50    EXIT                                          *SET MODE B                                                                   02F1 17 P90      INCB                                                         02F2 37          LD                                                           02FB 1E          SKZ                                                          02F4 A6          T       P80    NOT ZERO NUM-                                                                 BER - PRINT                                                                   ROW                                           02F5 26          RF1     *      CLEAR MODE A                                  02F6 21          SF2     *      SET MODE B                                    02F7 98          T       P50    EXIT                                                  *                                                                                      ORG     340                                                  *                                                                             *                                                                             *                                                                             *CONTINUE WITH GROUP/CALL KEY PROCESSING                                      *THE STORY SO FAR-                                                            *SCREEN ERASED, NO NUMBER DEALT WITH                                          *CONVERT DECIMAL TO BINARY NUMBER                                             0340 C3 XGPCL    R7D2                                                         0341 D4          TM      CLEAR  INITIALISE                                                                    BINARY TO ZERO                                0342 3F          EX                                                           0343 38          EX      7      GET GROUP                                                                     BITS 8/9                                      0344 3F          EX                                                           0345 37          LD      *      SHIFT TWICE                                                                   RIGHT & INSERT                                                                IN GROUP                                      0346 0B          AD                                                           0347 3F          EX                                                           0348 37          LD                                                           0349 0A          ADC                                                          034A 3F          EX                                                           034B 37          LD                                                           034C 0A          ADC                                                          034D 2B          EXD     4                                                    034E 8F          T       *+1                                                  0347 7F          LDI     0                                                    0350 3F          EX      *      INITIALISE POINTER                                                            FOR KBD *                                                                     DIGITS                                        *ADD IN NEXT DIGIT TO NUMBER SO FAR                                           0351 7E DB20     LDI     1                                                    0352 0B          AD      *      INCREMENT POINTER                             0353 38          EX      7                                                    0354 10          XABL                                                         0355 17          LD      *      GET NEXT DIGIT                                0356 03          LB      R7D2                                                 0357 24          RC                                                           0358 9A          T       DB40                                                 0359 7F DB30     LDI     0      ADD ANY CARRY                                 035A 0A DB40     ADC                                                          035B 2F          EXD                                                          035C 99          T       DB30                                                 *CHECK COMPLETION                                                             035D 34          LD      3                                                    035E 37          LD                                                           035F 62          ADI     D                                                    0360 A3          T       DB60   NOT ALL DIGITS                                                                DONE                                          0361 53 80       TL      DB90   FINISHED                                              *                                                                     0363 D1 DB60     TM      STORE  WAIT                                          *MULTIPLY NUMBER SO FAR BY 10                                                 *(MAKE ROOM FOR NEXT DIGIT)                                                   0364 D2          TM      SHIFT  *2                                            0365 C3          LB      R7D2                                                 0366 34 DB70     LD      3      SAVE *2                                       0367 2C          EXD     3                                                    0368 A6          T       DB70                                                 0369 D2          TM      SHIFT  *4                                                    *                                                                     036A D1          TM      STORE  WAIT                                                  *                                                                     0368B D2         TM      SHIFT  *8                                            036C 00 BD       LBL     D2R4   ADD *2                                        036E 24          RC                                                           036F 34 DB80     LD      3                                                    0370 0A          ADC                                                          0371 2C          EXD     3                                                    0372 AF          T       DB80                                                 0373 91          T       DB20   DO NEXT DIGIT                                                  ORG     380                                                          *                                                                     0380 D1 DB90     TM      STORE  WAIT                                          *COMPLETION                                                                   0381 CB          LB      R0D9                                                 0382 37          LD                                                           0383 6A          ADI     5                                                    0384 86          T       *+2    FROM GROUP                                    0285 8C          T       DB120  FROM CALL                                     0386 C3          LB      R7D2                                                 0387 30 DB100    LD      7                                                    0388 28          EXD     7                                                    0389 87          T       DB100                                                038A C3          LB      R7D2                                                 038B D4 DB110    TM      CLEAR  CLEAR PAGE #                                  038C 00 FF                                                                            DB120    LBL     DORO   RESET GROUP                                                                   BITS 8/9                                      038E 37          LD                                                           038F 0B          AD                                                           0390 0B          AD                                                           0391 0B          AD                                                           0392 3F          EX                                                           0393 30          LD      7                                                    0394 0F          OR                                                           0395 3F          EX                                                           *SEND NEW GROUP/PAGE TO TERMINAL                                              0396 D1 SEND     TM      STORE  WAIT                                                  *                                                                     0397 D6          TM      PEND   STOP PRINTING                                         *                                                                     0398 D1 SD10     TM      STORE  WAIT                                          *SEND PAGE #                                                                  0399 C3          LB      R7D2                                                 039A 24          RC      *      MARK PAGE #                                                                   SENDING                                       039B 34 SD20     LD      3      GET 4 BITS FOR                                                                GAD/PAD                                       039C 1C 1E       IOL     #1E    SEND                                          039E 42          SFBI    2                                                    039F A4          T       SD24   NOT 1ST 4 BITS                                03A0 15          SKC                                                          03A1 7E          LDI     1      1ST 4 BITS PAGE #                             03A2 77          LDI     *      1ST 4 BITS                                                                    GROUP #                                       03A3 AB          T       SD32                                                 03A4 15 SD24     SLC                                                          03A5 AS          T       SD30   2ND/3RD 4 BITS                                                                PAGE #                                        03A6 53 CO       TL      SD40   LAST 4-BITS                                                                   GROUP #                                       03A8 41 SD30     S4BI    1                                                    03A9 7B          LDI     4      3RD 4 BITS                                                                    PAGE #                                        03AA 7D          LDI     2      2ND 4 BITS                                                                    PAGE #                                        03AB 1C 07                                                                            SD32     IOL     #7     PULSE LEN                                     03AD 7F          LDI     0                                                    03AE 1C 07       IOL     #7                                                   03B0 2C          EXD     3                                                    03B1 9B          T       SD20                                                         *                                                                     03B2 D1          TM      STORE  WAIT                                          *SEND GROUP #                                                                 03B3 C1          LB      ROD2                                                 03B4 20          SC      *      MARK GROUP #                                                                  SENDING                                       03B3 9B          T       SD20                                                                  ORG     3CO                                                  03CO 77 SD40     LDI     8                                                    03CI D3          TM      PLSB                                                 03C2 1C 13       IOL     #13    GET PER                                       03C4 3F          EX                                                           03C5 7D          LDI     2                                                    03C6 0D          AND                                                          03C7 60          ADI     F                                                    03C8 9C          T       SD45   INVALID GROUP                                 03C9 C5          LB      R7D3   PER OK                                        03CA 2F          EXD                                                          03CB 1E          SKZ     *      INITIALISING                                  03CC 91          T       SD44                                                 03CD 7D          LDI     2      .                                             03CE 3F          EX      *      CALL PAGE 2                                   03CF 53 98                                                                            SD43     TL      SD10   SEND                                          03D1 D5 SD44     TM      SCHRS  RESET SCH'S                                           *        .                                                            03D2 D1 RESET    TM      STORE  WAIT                                          *RESET KBD # AND EXIT                                                         03D3 7F          LDI     0                                                    03D4 1C 17       IOL     #17    CLEAR KAC                                     03D6 C4          LB      R3D2                                                 03D7 D4 RS10     TM      CLEAR                                                03D8 70          LDI     F                                                    03D9 3F          EX                                                           03DA 53 10       TL      KBX25  RETURN TO                                                                     SCHEDULER                                     *INVALID GROUP - SET TO ZERO                                                  03DC C5 SD45     LB      R7D3   PER BAD                                       03DD 09          ADSK                                                         03DE 8F          T       SD43   INITING - RESEND                                                              PGE 1                                         03DF 1F          DECB                                                         0SEO 7C          LDI     3      BAD GRP - SEND                                                                GRP 0 PGE 3                                   0BE1 7F SD60     LDI     0                                                    0BE2 38          EX      7                                                    0BE3 7F          LDI     0                                                    0BE4 28          EXD     7                                                    0BE5 A1          T       SD60                                                 0BE6 8F          T       SD43                                                         *                                                                             *                                                                             *                                                                                      END                                                          ______________________________________                                    

The various inputs and outputs to the microcomputer or CPU 601 are allpreferably conventionally routed through the input/output buffer 607 forinterfacing the system with the microcomputer 601 and have been omittedfrom FIG. 27 for clarity; however, these signals as well as theirfunction in the system for providing displayable rows of videoinformation on video display terminal 2013 is illustrated in FIGS. 24,26 and 28 and shall be described in greater detail hereinafter. Duringoperation of the system, microcomputer 601 gets the instructionsrequired from the stored program in read only memory 603 step-by-step,such as "take data from buffer 607 and put in in random access memory605" or "take data out of random access memory 605 and provide it tobuffer 607". Microcomputer 601 can also perform typical computerfunctional operations on the data. As shown and preferred in FIG. 26which is a block diagram of the terminal key board and microprocessorinput/output for video display row-by-row of pseudo video scan lines inthe improved row grabbing terminal 28 of the present invention, thekeyboard 5000 provides selection information to the microprocessor 6000,such as the group and page address, as described in our previous U.S.Pat. No. 3,889,054. The balance of the circuitry of the receiver 28controlled by the microprocessor 6000 is generally represented by theblock 8000 labeled "terminal" in FIG. 26. If desired, the input/outputbuffer 607 may also include a conventional special character decoder inaddition to the balance of the interface functions performed thereby soas to detect the presence of a special character. The various latchingspreferably occurring within the terminal 8000 shall be described ingreater detail hereinafter with reference to FIG. 24. As shown andpreferred in FIG. 10, the keyboard entry line for the microprocessor6000 from keyboard 5000 preferably comprises four lines 6001, 6003, 6005and 6006 which are set when a key is pressed and latched and are resetto the idle state only when a clear pulse is sent via line 6007 from themicroprocessor 6000. The keys which can be set are numeric keys as wellas special function keys such as group, page, up, back, and call. Inaddition, as described in the copending U.S. Pat. application of RobertH. Nagel, one of the joint inventors herein, and owned by the sameassignee as the present application and entitled "Information RetrievalSystem Having Selectable Purpose Variable Function Terminal" filed Sept.10, 1975, and bearing U.S. Ser. No. 611,927 .Iadd.now U.S. Pat. No.4,064,490.Iaddend., additional keys such as program may be provided whenthe system is utilized to retrieve programs or sets of instructions asopposed to or in addition to data. As shown and preferred in FIG. 26, ifa group key is depressed and preceded by a number, terminal 8000 will beinformed of the new group via the group address and page address lineGAD/PAD and LEN lines, with the page number preferably reset to zero. Ifthe group is not preceded by a number, preferably the only action takenwould be to release directed messages by setting and clearing the KACline and to erase the screen via a pulse on the ERA line, all functionswhich change the group/page accomplishing this such as call, back, upand group. The inputs from the terminal 8000 to the microprocessor 6000are preferably the row enable line REN, the row address read line RAR,the row address write line REW, the special character line SCH, and thepermission line PER. The output to the keyboard is preferably the clearor keyboard latch reset line 6007 which is pulsed when a key has beencompletely processed so that the key will then be reset to the idlestate. The outputs to the terminal 8000 from the microprocessor 6000preferably comprise the erase line which erases the video display 2013,the keyboard active line KAC which is set while a group/page number isbeing sent to the terminal 8000 so that the terminal 8000 will take noaction on it until the number is completely received, the groupaddress/page address line GAD/PAD which informs the terminal 8000 of anew page to grab, the latch enable line LEN and the row length line RWL.Suffice it to say that the microprocessor 6000 performs all datahandling and execution of the permanently stored program in the readonly memory 603 with the random access memory 605 preferably functioningto store data in order to accomplish the row grabbing function, the databeing taken out of the random access memory 605 and provided to theinput/output buffer 607 for subsequent display on the video display2013.

Referring now to FIG. 24, the output of microprocessor 6000 preferablyincludes four general purpose address bits or lines 715 and five linesof enable pulses 717. Lines 717 specify which one of the plurality oflatches 701, 703, 705, 707 and 709, collectively referred to byreference numeral 699, with latches 701, 703 and 705 being the pageaddress latches, and latches 707 and 709 being the group addresslatches, the address bits 715 are designated for. By utilizing the fourdata lines 715 and five enable lines 717, up to 20 different bits ofaddress, which is equivalent to 1,048,576 addresses, can be established.The page address output bits collectively referred to by referencenumeral 504 and the group address output bits collectively referred toby reference numeral 502 are employed in the memory input controlportion of the receiver 28 illustrated in FIG. 11 preferably in the samemanner as described in our previous U.S. Pat. No. 3,889,054 with respectto the outputs of the keyboard counter 500 of the system described inU.S. Pat. No. 3,889,054 and will not be described in greater detailhereinafter since such description is specifically incorporated byreference herein.

Referring to the aforementioned exemplary program written in PPS-4Assembler language, as was previously mentioned, a typicalmicroprocessor 6000 arrangement which is controlled by theaforementioned program is illustrated in FIG. 28 with the various pinnumber designations utilized by Rockwell International for the read onlymemory, random access memory, CPU or microcomputer, and input/bufferchips 605, 603, 601, and 607a and 607b, respectively being utilized inFIG. 28 for clarity. Furthermore, and as shown and preferred in FIG. 26,if desired, the receiver terminal 28 may additionally have acomputer/printer or cathode ray tube display interface for use with aCRT character generator so as to provide a "hard copy" printout of theinformation being displayed on video display 2013 as well as the videodisplay thereof. However, this is optional to the improved video displayterminal of the present invention and need not be included unless such"hard copy" printout is desired. In such an instance, a printerinterface 8004 and conventional printer 8006 would be required and wouldpreferably be controlled by the microprocessor 6000 in a manner to bedescribed in greater detail hereinafter. It should be noted that if suchprinting function is not desired then the functions of the terminal 28and microprocessor 6000 relating thereto may be omitted; however, forpurposes of completeness the programmed terminal will be described, asillustrated in the aforementioned program, assuming such printer andprinting function is included.

Referring once again to FIGS. 26 and 28 and the aforementioned program,in order to facilitate the understanding of the functioning of theillustrative conventional program in the system of the presentinvention, the following detailed description of the inputs from thekeyboard 5000, the inputs from the printer interface 8004, the inputsfrom the terminal 8000, the outputs to the keyboard 5000, the outputs tothe printer interface 8004, the outputs to the terminal 8000, theinput/output buffer assignments, the random access memory or RAMallocations, the register allocations, and the read only memory or ROMmay be provided by way of example below.

Inputs (from keyboard 5000) a. Keybard entry KEY 4 lines

Set when a key is pressed and latched. Reset to the idle state only whena pulse sent on KLR. Settings are as follows:

0-9: for numeral key. Consecutive numeral keys pressed will build anumber (leading zeros automatically provided). Leading digits whichcause the number to become too big for the function will be ignored -e.g., if 255 is the biggest number allowed for a group, and the number256 is inserted, when the GROUP key is pressed, this will be truncatedto 56.

A₁₆ : for GROUP key. If this is preceded by a number, the terminal willbe informed of the new group via GAD/PAD and LEN lines, with page numberreset to zero. If not preceded by a number, the only action taken willbe to release directed messages by setting and clearing KAC and to erasethe screen via a pulse on the ERA line (all functions which change thegroup/page do this - i.e., CALL, BACK, UP and GROUP). Biggest numbersare 127 for 6-bit characters, 1023 for 7-bit characters.

B₁₆ : for PRINT key. There are two print modes - mode A is initiated bypressing the PRINT key preceded by a number between 1 and 16 (whentruncated to=16), or by pressing the print key with no preceding numberwhen not already in mode A or B. The former will cause the specified rowof the displayed page to be printed, preceded and terminated by a linefeed, carriage return.

The latter will cause the complete page to be printed, preceded by aline feed, carriage return, and each row terminated by a line feed,carriage return. Several rows can be marked for printing before thefirst has been fully printed by repeating the row print command.

Mode A is terminated by the printing initiated above being completed, orby pressing the PRINT key with no preceding number when already in ModeA or B (this also terminates Mode B), or by doing an operation whichsends a new GAD/PAD identifier pulse (i.e., pressing valid GROUP, CALL,UP, BACK) or by starting Mode B.

Mode B is initiated by pressing the PRINT key preceded by the number 0(when truncated). This prints certain information on receipt of certainSCH's (see below). It is terminated by pressing the PRINT key precededby a non-zero number (which initiates Mode A), or by pressing the PRINTkey with no preceding number when already in Mode A or B (this alsoterminates Mode A).

C₁₆ : for UP key. Any preceding number is ignored. The page number isincremented and the terminal informed via GAD/PAD and LEN lines with thegroup number unchanged. The screen is first cleared by an ERA pulse. Ifthe page number is already at its highest limit (1023 for 6-bitcharacters, 4095 for 7-bit characters) the key pressing is ignoredexcept for the screen being cleared, and KAC being set and cleared torelease directed messages.

D₁₆ : for BACK key. As UP except the page number is decremented, and noaction is taken if the page number is already zero.

E₁₆ : for CALL key. If this is not preceded by a number, zero isassumed. Else, the number is truncated to ≦1023 if the central computeris transmitting 6-bit characters (determined by SCH values - see below),or ≦4095 if 7-bit characters are transmitted. The page number is resetto this and the terminal informed in GAD/PAD and LEN lines, with thegroup number unchanged. The screen is first cleared by an ERA pulse.

F₁₆ : when in idle state. When any key is pressed that key is notprocessed unless it is held constant for a minimum of 1 millisecond, toprovide bounce protection.

As KEY is not reset to idle state unless the key has been released andKLR has been pulsed, KEY is not processed unless it is different fromthe last KEY processed, although KLR will be periodically pulsed.

Inputs (from printer interface 8004) b. Printer character clock PCC 1line

Runs at the printer rate (10 cps). High for 27 milliseconds (3-bittimes) during which stop and idle bits are sent to printer and wheninterface can receive a pulse (SPA, LFD, CAR or PRT) from the PPS. Lowfor 73 milliseconds during which a character is sent to the printer.Used to determine when to send one of the above pulses to the interface,and also as a count after a PRT pulse is issued to determine when a rowhas been printed.

Inputs (from terminal 8000) c. Row enable REN 1 line

Runs at the row rate of the terminal. 1 row = 13 scan lines = 13*63microseconds (except during vertical retrace ≅ 5 milliseconds). Lowwhile RAR changing and therefore invalid (especially during verticalretrace). High when RAR valid.

d. Row address (read) RAR 4 lines

When REN is high, contains the address (O→ 15) of the row currentlybeing read from memory and displayed on the screen, and available fortransmission to the printer interface. The printer interface must betold to accept the row, if it is the correct one, within 3 scan lines (=3*63 microseconds) of RAR changing, by a PWR pulse.

e. Row address (write) RAW 4 lines

Contains the address 80→ 15) of the last row written to memory afterbeing grabbed from the cable. It is latched onto this and will notchange until a new row is read. As rows can preferably only be writtenduring the 3 blank scan lines at the end of a row, this will only change2 scan lines (110μsec = 22 cycles) before RAR changes. RAW willtherefore be constant for a minimum of 10 scan lines after RAR changes.

f. Special character SCH 7 lines

Each row written (see RAW) has an SCH attached to it. This is changed atthe same time as RAW and latched. Characters transmitted by the centralcomputer are either 6 or 7 bits. To enable the PPS to known which, atleast one row on Group 0, Page 0 will be transmitted with an SCHindicating which by its most significant bit (= 0= > 6-bit chars, = 1= >7-bit). As group and page are automatically set to zero on power up, thePPS will known, from the very first page grabbed, what limits to set forpage and group. Apart from this SCH, at the moment all other SCH's haveindividual meanings as follows:

0: Reset. Set to 0 by the terminal on power up. Real SCH's are zero whenno action is to be taken, or when action started by an SCH is to berepeated. To ensure that action on any SCH is taken, the centralcomputer will repeat it on the particular row several times. So toensure a desired single operation is not repeated, the PPS will only acton an SCH which has changed on that row. Therefore, to repeat a similaroperation, the central computer must send a zero SCH on the row beforerepeating the non-zero SCH. When a new page is selected, the PPS willact on the first SCH on each row, and then only when an SCH for a rowchanges.

1: Row print (select). The row specified by RAW is printed only if inprint mode B.

2: Page print (select). The page displayed is printed only if in printmode B.

3: Row print override. The row specified by RAW is printed regardless ofprint mode.

4: Page start. Not used for any specific PSS function.

8: 64character row. The row specified by RAW is a 64 character row. Ifthis row is printed later on, the PPS will wait for 64 clock pulsesafter issuing a PRT pulse before it sends the terminating LFD, CARpulses. Receipt of this SCH sets RWL to 1.

10₁₆ : 32 character row. The row specified by RAW is a 32 character row.If this row is printed later on, the PPS will send 16 SPA pulses (tospace the row in the middle of the page), then a PRT pulse. After 3clock pulses, it sends the terminating LFD, CAR pulses. Receipt of thisSCH sets RWL to 0.

18₁₆ : Erase. The PPS sends an ERA pulse to the terminal.

g. Permission PER 1 line

After a new group number is sent to the terminal this line is tested. Iflow, the terminal is not allowed to receive that group, so the groupnumber is reset to zero (the page number will already be zero), andreset to the terminal. The line is valid at any time, even when KAC isstill set.

Outputs (to keyboard 5000) a. Keyboard latch reset KLR 1 line

Pulsed when a key has been completely processed. KEY will then be resetto the idle state.

Outputs (to printer interface 8004) b. Printer write PWR 1 line

When a print is initiated, RAR is sampled until it equals the next rowto be printed. PWR is pulsed within 189 microseconds of it changing, sothe interface can write the row into its memory for printing on the PRTpulse.

c. Space SPA 1 line

On a 32 character row print, 16 leading spaces are printed, by sendingthis pulse once during each clock cycle when PCC is high for 16 times.

d. Line feed LFD 1 line

To print line feed, send LFD pulse while PCC high.

3. Carriage return CAR 1 line

To print carriage return, send CAR pulse while PCC high.

f. Print PRT 1 line

To print the row currently held in the printer interface buffer, sendPRT pulse while PCC high and wait 32 or 64 clock times before issuingany other pulse to the interface.

Outputs (to terminal 8000) g. Erase ERA 1 line

Erases screen. Pulse when SCH 18₈ received, or when a group/page numberis sent to the terminal, or when GROUP key is pressed with no precedingnumber.

h. Keyboard active KAC 1 line

Set while a group/page number is being sent to the terminal, so theterminal takes no action on it until the number is completely received.Will always be preceded by an ERA pulse. Also ensures directed messagesare released, so set and cleared for any pressing of GROUP, CALL, BACKor UP, even if no new group/page number is sent.

    ______________________________________                                        I/O Assignments (bit 0 = LSB, bit 3 = MSB)                                    ______________________________________                                        I/O 0.sub.(607a)                                                                      GRP A    (A) READ  SCH bits 0-3                                                        (E) SET   SPA (bit 0), PRT 1,                                                           1), LFD (bit 2), CAR (bit 3)                               GRP B    (9) READ  KBD                                                                 (D) SET   PWR (bit 0), KLR (bit 1),                                                     ERA (bit 2), LEN bit 4 (bit 3)                                                (Only used for pulse via TM                                                   PLSB.)                                                     GRP C    (3) READ  RAW                                                                 (7) SET   LEN bits 0-3                                       I/O 1.sub.(607a)                                                                      GRP A    (1A) READ SCH bits 4-6 (bits 0-2). Ex. 3                                                always 1. 0.                                                        (1E) SET  GAD/PAD                                                    GRP B    (19) READ RAR                                                                 (10) SET  RWL (bit 0)                                                                   (Any change of bits 1-3 must                                                  leave RWL unaltered).                                      GRP C    (13) READ PER (bit 1), PCC (bit 2), REN                                                 (bit 3)                                                             (17) SET  KAC (bit 1)                                                                   (Any bit set excludes others                                                  from being set).                                   ______________________________________                                    

Group address/Page address GAD/PAD 4 lines

To inform the terminal of a new page to grab, the page's identifier issent in 5 pulses of 4 lines each. Afer the identifier is assembled inthe PPS, the first 4 bits will reset on these lines, and LEN line 1 ispushed. Then the second 4 bits are set, and LEN line 2 is pulsed, and soon until all 20 bits are sent. The identifier is constructed from thegroup/page number as follows:

i. using 6-bit characters

bits 0→9=page number

bits 10/11=0

bits 12→18=group number

bit 19=0

ii. using 7-bit characters

bits 0→9=page number

bits 12→19=group number bits 0→7

bits 10/11=group number bits 8/9

j. Latch enable LEN 5 lines

Only 1 line pulsed at any one time. If line n is pulsed, the terminalwill take the 4 GAD/PAD lines as the nth 4 bits of the new group/pageidentifier (20 bits).

k. Row length RWL 1 line

Latched on 1 for 64 character rows, 0 for 32 character rows. Setaccording to the last SCH of 8 or 10₁₆.

    ______________________________________                                        RAM (605) allocation (RxDY = RAM address xy)                                  (all initially zero unless otherwise stated)                                  ______________________________________                                        R0    D0/1/2   Group # [3rd digit - bits 8/9 - only used as tem-                             porary storage as bits 8/9 group # normally held                              in page #]                                                     Also  D0/1/2   Page # [bits 10/11 = bits 8/9 group #]                                        used for binary # during decimal to binary                                    conversion                                                     R3    D0/1/2/3 Keyboard # (decimal) R3D0 = F.sub.14 = > no                                   number yet/ R3D0 = most significant digit                      R4    D0/1/2/3 Workspace. Used for current high limit and                                    during decimal to binary conversion.                           R8    D0/1/2/3 Group # high limit (decimal). Initially 0, 1, 2, 7.            R9    D0/1/2/3 Page # high limit (decimal). Initially 1, 0, 2, 3.             R6    D0/1/2   KBD routine suspend address - used by STORE                                   S/R. Initally complement of address of                                        KBYX (C, F, F).                                                R1/R2          Complement of last SCH on each row. (R1 =                                     bits 0-3, R2 = bits 4-7)                                       R5             Row status for each row:                                                      Bit 3 set = > print this row                                                  Bit 2 set = > print leading CRLF                               R3    D5       Current row - set to row being searched for,                                  or row being printed.                                          R6    D5       Row count # of rows searched for without being                                printed.                                                       R4    D5       Searching for row                                                             = 0 = > yes                                                                   = 1 = > no Initially 1                                         R3/R4 D6       6-bit count for printing. Used when printer pulse                             occurs and printing in progress.                                              If = 0, next o/p is shifted left and if ≠ 0, that                       pulse is sent (if = 2 when shifted, new count is                              set also).                                                                    If when shifted, next o/p = 0, then next row to                               print is searched for.                                                        If ≠ 0, next o/p is masked with mask and that                           pulse sent after the count is decremented.                     R0    D7       Row length = F = > 64 char rows = E =                                         > 32 char rows. Set by last SCH of 8 or 10.sub.14.             R3    D7       Next o/p                                                                      = 1 = >SPA] ≠ 0 = > printing in progress                                = 2 = >PRT] = 0 = > no printing                                               = 4 = >LFD]                                                                   = 8 = >CAR]                                                                   This digit is sent on I/O 0 group A as a pulse                                after being masked or shifted as above.                        R4    D7       Mask                                                                          = 0 = > Do not send SPA or PRT pulse unless                                   count = 0 (then no mask takes place).                                         64 character rows (set when row to                                            be printed)                                                                   = 1 = > Do not send PRT pulse unless count                                    = 0. 32 character rows                                                        [Remember when count = 0, shift left of next o/p                              occurs before pulse.]                                          R3    D8       Last PCC valve (in bit 2).                                     R4    D8       4 (constant mask for above). Initially 4                       R0    D9       Current KBD character.                                         Register Allocation                                                           FF1             = 1 = > Print mode A (KBD printing)                           FF2             = 1 = > Print mode B (SCH printing)                           X               Temporary working space                                       R3    D9        KBD count                                                                     = 0 = > KBD character can be processed                                        ≠ 0 = > No. of program loops to go before                               KBD character is accepted (bounce                                             protection)                                                   R4    D9        Complement of last KBD character                              R3    D10       Complement of last RAR                                        R4    D15       Workspace used to access each digit in                                        binary to decimal conversion                                  ______________________________________                                    

    __________________________________________________________________________    ROM (608) Map                                                                 Page    Description               Spare Words                                 __________________________________________________________________________    0   (00)        Initialization (63)                                                                             1                                           1   (40)        Check RAR/SCH/RAW                                                                            (43)                                                           Check RAR      (17)                                                                             5                                           2   (80)                                                                              Scheduler                                                                             Check PCC      (61)                                                           Go to KBD check                                                                              (1)                                                            Return to start of scheduler                                                                 (2)                                                                              0                                           3   (C0)        RAM addresses (1st 16 words)                                                                 (16)                                                                             0                                                           S/R addresses (last 48 words)                                                                (26)                                                                             22                                          4   (100)       Go to SCH decoder                                                                            (2)                                                            Switch S/R     (7)                                                            Binary shift left S/R                                                                        (7)                                                            Stop printing S/R                                                                            (7)                                                            Pulse I/O 0 group B S/R                                                                      (6)                                                            Suspend S/R    (6)                                                            KBD decoder S/R                                                                              (23)                                                                             6                                           5   (140)       Get row S/R    (35)                                                           SCH row print [3 S/R's]                                                                      (27)                                                                             2                                           6   (180)       SCH page print [2 S/R's]                                                                     (19)                                                           SCH erase [2 S/R's]                                                                          (8)                                                            SCH row length [2 S/R's]                                                                     (10)                                                           SCH character length S/R                                                                     (10)                                                           Clear 3 digits S/R                                                                           (7)                                                                              2                                                           Reset special characters                                                                     (8)                                            7   (1C0)       KBD numeral S/R                                                                              (7)                                                            KBD up S/R     (28)                                                           KBD back S/R   (21)                                                           Go to KBD call (2)                                                            Go to KBD group                                                                              (2)                                                            Go to KBD print                                                                              (2)                                                                              2                                           8   (200)       SCH decoder switch jump                                                                      (1)                                                                              63                                              (240)       SCH decoder table                                                                            (128)                                                                            0                                           10                                                                            11  (2C0)       KBD print S/R  (56)                                                                             8                                           12  (300)       Check KBD      (23)                                                           RAR check - print row                                                                        (36)                                                           RAR check - get row                                                                          (2)                                                                              3                                           13  (340)       KBD group S/R  (11)                                                           KBD call S/R (Pt 1)                                                                          (50)                                                                             3                                           14  (380)       KBD call S/R (Pt 2)                                                                          (57)                                                                             7                                           15  (3C0)       KBD call S/R (Pt 3)                                                                          (60)                                                                             4                                           __________________________________________________________________________

It is of course understood that the above program and programdescription is merely provided by way of example and other programs andprogram arrangements could be utilized to accomplish the row grabbingvideo display function of the present invention without departing fromthe spirit and scope thereof. In addition, as previously mentioned, ifdesired a conventional keyboard control system such as described in ourprevious U.S. Pat. No. 3,889,054 could be utilized in the improved rowgrabbing system of the present invention in which instance themicroprocessor 6000 and the associated programming required thereforwould be omitted. It should be noted that with respect to FIG. 10 whichillustrates the keyboard 5000, the keyboard key switches 823 andassociated lines 823a through 823d with their respective associatedflip-flop latches 824, 825, 826 and 827, respectively, which are clearedby the signal present on path 6007, are preferably indentical inoperation with that previously described in our previous U.S. Pat. No.3,889,054 which description is specifically incorporated by referenceherein.

Similarly, referring to FIG. 13 which illustrates a portion of theimproved memory output processor portion of the receiver 28 of thepresent invention, this portion is preferably identical with thatdescribed in our previous U.S. Pat. No. 3,889,054 with the exception ofthe erase circuit and the special character latching functions utilizedwith 32-or 64 character selection, to be described in greater detailhereinafter with reference to FIG. 13. Identical reference numerals areutilized for identically functioning components in FIG. 13 with thosepreviously described in our previous U.S. Pat. No. 3,889,054 withreference to FIG. 12 of that patent which description was specificallyincorporated by reference herein and will not be repeated. It should benoted that reference numeral 901 represents a special character latch,with the fifth character preferably being the special character, and,accordingly, latch 901 is strobed via path 903 during the fifthcharacter. Any time a new valid pseudo video scan line s received, thespecial character, which is as previously mentioned preferably the fifthcharacter, of that pseudo scan line is entered into latch 901. Theoutput of latch 901 is preferably provided to microprocessor 6000, asrepresented by the symbol "SCH" to provide an input thereto. Preferably,microprocessor 6000 does not act on all special characters such as forexample not acting with respect to 32-or-64 character selection,although, if desired, the microprocessor could also be programmed toaccomplish this.

ERASE CIRCUIT

Now considering the improved erase circuit portion 905 of the memory andoutput processor portion illustrated in FIG. 13, the erase circuit 905provides a means for making the screen of the video display device 2013go blank. This is desirable at initial turn on at which time the mainmemory would come on with a random bit pattern which in turn woulddisplay a random assortment of characters which would be meaninglessand, perhaps, confusing to the viewer. Erase is accomplished by loadingall character locations in memory which comprises stages 1030 through1042 preferably with an octal 40 value which is the value whichcorresponds to a "space" in ASCII code. The erase cycle can be initiatedalso by the microprocessor 6000 in response to the appropriate specialcharacter assigned for the erase function or whenever a keyboard cycletakes place, if desired. The erase cycle is preferably initiated by aconventional flip-flop 907 which gets set initially when power is on asa result of an RC charging network 909 through inverters 911 connectedto the preset input of flip-flop 907. Flip-flop 907 can also preferablyget set by microprocessor 6000 via the clock input provided via path 913from microprocessor 6000. Once set, flip-flop 907 preferably enables aconventional two input NAND gate 925 which also receives the verticalsync pulse via path 923. Therefore, the first vertical sync pulse thatoccurs after flip-flop 907 is set appears as a negative pulse at theclock input of a second flip-flop 915 to which the output of gate 925 isconnected. Flip-flop 915 is clocked to its set state preferably at thetrailing edge of the vertical sync pulse. When set, the output offlip-flop 915 preferably switches a conventional multiplexer 917 such asa Texas Instruments SN 74157N, which accomplishes the switchingnecessary to load the memory octal 40 values; specifically, switch 917aand 917b illustratively shown separate in FIG. 13 actually comprise themultiplexer 917 with switch 917a of multiplexer 917 loading a logic oneinto the correct bit position of character latch register 468 whoseoperation is described in detail in our previous U.S. Pat. No.3,889,054, to obtain octal 40 therefrom. All of the other bits arepreferably set to 0 via path 919 which is connected to the invertedoutput of flip-flop 915 with the signal present thereon turning off theinput to shift register 466 previously described in detail in ourprevious U.S. Pat. No. 3,889,054, via a conventional two input NAND gate921 whose inputs are the output of shift register 457, which is alsopreviously described in our U.S. Pat. No. 3,889,054, and the invertedoutput of flip-flop 915. As a result, all logic zeros are present at theoutputs of shift register 466 which logic zeros are provided to theinputs of character latch register 468 except for the previouslymentioned single bit. Switch 917b of multiplexer 917 switchesmultiplexer 1020, which is described in detail in U.S. Pat. No.3,889,054, so that the read row addresses are applied to the memorystages 1030 through 1042 even though the memory stages 1030 through 1042are in the write mode during the erase cycle. This insures that allmemory locations are addressed during erase. Termination of the erasecycle is preferably accomplished by the second vertical sync pulse thatoccurs after flip-flop 907 has been set. The second vertical sync pulseclocks flip-flop 915 back to its original state and also clearsflip-flop 907 via another conventional two input NAND gate 927 whoseoutput is provided to the clear input of flip-flop 907 through aninverter 929. Thus, both flip-flops 907 and 915 are returned to theiroriginal state. The period of the erase cycle is thus preferably onevertical field period, this time being adequate to insure that allmemory stage locations 1030 through 1042 have been addressed. As waspreviously mentioned the balance of the circuitry illustrated in FIG. 13is adequately described in detail in our previous U.S. Pat. No.3,889,054 which was specifically incorporated by reference herein.

PERMISSION MEMORY CIRCUITRY

Referring now to FIG. 12, the improved permission memory circuitryutilized in the preferred improved row grabbing terminal 28 of thepresent invention shall be described in greater detail. Except whereotherwise specifically noted, the portions of the circuit in FIG. 12 arepreferably identical with the permission memory circuitry described inour previous U.S. Pat. No. 3,889,054 with reference to FIG. 11 of thatpatent and identical reference numerals are utilized therefor. Thus,this description which is incorporated by reference herein will not berepeated and the following discussion of the improved permission memorycircuitry will primarily be directed to the differences over thepermission memory circuitry described in U.S. Pat. No. 3,889,054. In theprevious permission memory circuit of U.S. Pat. No. 3,889,054, counters974 and 976 were initially cleared to zero rather than being preloadedto a predetermined number such as 254. Thus, this previous system couldpossible provide a couple of extraneous clock pulses before the firstpermission bit was received so that the counter was at a value of onewhen the first permission arrived and, accordingly, group 0 would not beavailable. In the improved permission memory circuit shown in FIG. 12,counters 974 and 976, which are four bit counters, constitute a 256 bitcounter, although if desired a 128 bit counter could be utilizedinstead. This counter, which is comprised of counters 974 and 976, ispreferably utilized for addressing the permission memory 462 during thepermission write cycle. Counters 974 and 976 are preferably initiallyloaded to a predetermined value, such as preferably 254, which isaccomplished by utilizing the load input 931 of counter 976 inconjunction with the preset inputs 933a and 933b of counters 974 and976, respectively. As a result of the preload via path 931, at thebeginning of a permission write cycle, the first two clock pulsesadvance the counter 974-976 to 0. The second clock pulse occurs justprior to the availability of the first permission bit. This timingsequence makes it possible for the first permission bit to representgroup 0. Thus it is possible to insure permission for groups 0 through127 on one pseudo video scan line. As shown and preferred in FIG. 12,128 groups are provided via the connection of permission memory 462;however, as will be described in greater detail hereinafter, if desired,additional counters may be provided in conjunction with permissionmemory 462 so as to provide up to 1000 groups.

The improved permission memory circuit illustrated in FIG. 12 alsoenables self-termination of permission write to return the system to thenormal mode of a permission line occurs at the end of a field. This isaccomplished in the following manner. An inverter and NAND gateconstitute a decoder 935 that generates a pulse preferably at a count,such as 192, which is greater than the number of groups, which werepreviously mentioned as being 128 by way of example in the arrangementillustrated in FIG. 12, and less than the number of bits in a data lineto permission memory, which number of bits preferably constitutes 238 byway of example. The number 192 is preferably chosen for ease of decodingalthough it could be any number between 128 and 238, the criteria forthese limits being defined as being greater than the number of groupsand less than the number of bits in a data line to permission memory.This pulse is provided through an inverter 937 to an input of aconventional two input NOR gate 939 whose other input is the keyboardactive line 941 and whose output is utilized to reset the permissionflip-flop 960. The flip-flop 960 is guaranteed to get reset even if thecompletion of permission write occurs during vertical blanking. In sucha case, flip-flop 960 would not otherwise get reset because the decodedcharacter 41 pulse present on path 413 is not normally generated duringvertical blanking. During a keyboard cycle, the group address ispreferably not a valid signal. Therefore, the output of the permissionmemory 462 would not be valid. Accordingly, in order to prevent anerroneous authorization, flip-flop 960 is held in a reset state duringthe keyboard cycle. This is accomplished by the keyboard active line orKAC 941 which is generated by microprocessor 6000 which, as waspreviously described, is applied to the other input to NOR gate 939.Preferably, the improved permission memory of FIG. 12 providespermission initialization when the power is turned on, the permissionmemory circuit automatically selecting group 0, page 0 at such time.When the first permission line is received by receiver 28, thepermission memory circuit of FIG. 12 will then preferably revert tonormal operation. THis initial mode, group 0, page 0 on turn on, ispreferably established by flip-flop 953 which is initially preset byline 955 (FIG. 13) when power is turned on. The output of flip-flop 953is preferably applied to a conventional NOR gate 957 via line 959 andsets the permission O.K. line 556 through an inverter 961. This assertspermission. Line or path 959, which is also preferably connected to gate963 of the page address circuit (FIG. 11), and is termed pre-permission,also sets line 508 low. This simulates an address of page zero, groupzero.

Referring now to FIG. 14, the improved permission memory updatecircuitry for updating the permission memory 462 (FIG. 12) is shown andwill be described. As will be described in greater detail hereinafter,the purpose of the improved permission memory update circuitry is toavoid any flicker which might otherwise occur in the video display ondisplay device 2013 during update of the permission memory as a resultof such update. In the improved circuitry of FIG. 14, the previouslyconsidered clock B signal is replaced by the prime clock provided viapath 401 from the voltage controlled oscillator 130 (FIG. 3). This primeclock input provided via path 401 to the permission memory updatecircuitry is inverted by an inverter 965 and applied to a conventionalsingle-shot 967. Preferably, the purpose of single-shot or one-shot 967is to generate a symmetrical square wave which is required by theconventional frequency double circuitry comprising inverters 1074 and1076 and exclusive OR gate 1078. As described in our previous U.S. Pat.No. 3,889,054, inverters 1074 and 1076 provide a predetermined delay,such as 100 nanoseconds in the prime clock signal provided via path 401,this delay time preferably representing a fraction of the clock period.It is this delayed prime clock signal which is preferably supplied toone input of the two input exclusive OR gate 1078 whose other input isdirectly connected to the prime clock input provided at the output ofsingle-shot 967. Exclusive OR gate 1078 preferably provides an outputonly during the period of time that the delayed prime clock signaloverlaps the undelayed prime clock signal, which occurs twice per clockperiod and, as a result, two output pulses are available from gate 1078for each input pulse. As shown and preferred in FIG. 14, the output ofexclusive OR gate 1078 is fed to a conventional switch 1079 whichselects between the 32 character position and the 64 character positiondepending on the desired character display, with the exclusive OR gate1078 output being connected to the 64 character position and thenon-doubled or direct prime clock signal being connected directly to the32 character position of switch 1079. The output of switch 1079 isprovided to the clock input of a conventional divide-by-eight counter1080 previously described in our U.S. Pat. No. 3,889,054, such as thetype manufactured by Texas Instruments under the designation SN74161N,which is a four bit binary counter connected as a divide-by-eightcounter, although, if desired, a conventional divide-by-eight countercould be utilized. Thus, the frequency doubled clock signal ispreferably utilized as the clock for counter 1080 only during 64character operation while, during 32 character operation, that is 32characters per video row versus 64 characters per video row, counter1080 is clocked directly by the prime clock signal. The prime clocksignal provided via path 401 is preferably unaffected by the permissionwrite mode (FIG. 8). The normal horizontal sync signal provided via path969 is preferably utilized for the horizontal timing of all of thedisplay circuits including the memory read circuit. The horizontal syncon path 969 is also unaffected by the permission write mode as it is thenormal sync during the permission write mode.

The clear signal for counter 1080 is preferably developed as follows.Counter 971 in conjunction with flip-flop 973 establishes the start of adisplay video row. During horizontal sync, counter 971 is preloaded to acount which depends on whether the terminal 28 is operating as a 32 or64 characters per row terminal. When the terminal 28 is operating as a32 character per row terminal, the perload condition for counter 971 ispreferably selected as one value, such as preferably 15, and when theterminal 28 is operating in the 64 characters per row mode the preloadfor counter 971 is preferably selected as another value, such aspreferably 11. Whichever value is selected, that value is selected so asto obtain the correct starting position on the display screen. Adifferent perload condition is preferably required for the 32 and 64characters per row modes because preferably a different clock frequencyis required for these two modes.

At the conclusion of the horizontal sync pulse, counter 971 preferablystarts counting at the prime clock rate which prime clock is provided tothe clock input of counter 971 from single-shot 967. At the completionof the count, the output of the two input NAND gate 975, which has oneinput connected to the noninverted output of flip-flop 973 and the otherinput connected in parallel to the clock input to flip-flop 973 prior toinversion thereof, goes low and stops the counting using the P inhibitinput of counter 971. Preferably a predetermined count value, such aspreferably a value of 31, terminates the count cycle. The negative levelpresent at the output of gate 975 is also provided in parallel throughan inverter 977 and applied to the clear input of counter 1080 whichenables counter 1080 by removing the clear state and counter 1080 startsits count sequence. Thus, by utilizing the prime clock for row one andthe normal horizontal sync 969 together with the improved circuitry forenabling counter 1000, the display circuits are preferably independentof the permission memory update and, thus, any flicker which mightotherwise occur in the display during such update as a result thereof isminimized and preferably avoided. The balance of the circuitryassociated with FIG. 14 is preferably identical with that described inour previous U.S. Pat. No. 3,889,054 with reference to FIG. 13 thereof.

MAIN MEMORY UPDATE

Referring again now to FIG. 12, the improved main memory updatecircuitry shall be described in detail hereinafter. Preferably, undernormal conditions when the main memory whih comprises stages 1030through 1042 (FIG. 13), is in the write mode, the outputs of thesestages 1030 through 1042 are not valid. Thus, as shown and preferred inFIG. 12, update control circuitry 979 is provided to prevent the mainmemory updating or writing if a valid pseudo video scan line is receivedwhile a row is being displayed. If a valid pseudo video scan line isreceived while a row is being displayed, other than during theoccurrence of dead space on the screen, this line will perferably bestored in shift register 457 (FIG. 13) until completion of thatdisplayed row and the line then would be written into memory 1030through 1042 during the dead space following the row. When a validpseudo video scan line is received, path 981, which is connected to theoutput of NAND gate 986, goes low and sets a flip-flop 983 which remainsset preferably until the display sweep completes the 12th line countedof a row which is equivalent to line 11 which is a preferably dead lineof a row with lines 1 through 9 of the row preferably being consideredactive lines for a row. The information corresponding to line 11 isprovided to a three input NAND gate 985 which decodes the count of 11provided from the output of line counter 1056 (FIG. 14) and provides anegative pulse to the clock input of flip-flop 983. Flip-flop 983 isthen preferably reset at the end of that pulse; that is, at thecompletion of the 12th line counted which is equivalent to line 11. Inthis regard, it should be noted that the zero line is the first linecounted and, therefore, the 11th line or a count of 11 is the 12th linecounted. The time during which flip-flop 983 is set preferablyestablishes the time during which the input data must be stored in theone line shift register 457 (FIG. 13) which preferably stores thisinformation as long as flip-flop 983 is set plus one more line to enablefor shifting out and writing into memory 1030 through 1042. Updatecontrol circuit 979 also preferably includes a two input NAND gate 987which has one input connected in parallel to the Q or non-invertedoutput of flip-flop 983 and the other input connected to the output ofNAND gate 983. The output of gate 987 is preferably provided through aninverter 989 to one input of another gate 991 whose other inut is thedata gate signal provided via path 993 from flip-flop 696 (FIG. 8). Theoutput of gate 991 is the gate hold signal which is provided via path997 to flip-flop 1002 (FIG. 13) and is the control line which stops theclocking of shift register 457 (FIG. 13) during the period thatflip-flop 983 is set excluding the 12th line counted; in other words,the output of gate 991 via path 997 goes low when a valid pseudo videoscan line is received and goes high at the beginning of the 12th linecounted, which is equivalent to line 11. The output of gate 991preferably cannot go high until the inverted data gate line 993 goeslow. This continues to hold data in the serial shift register 457 (FIG.13) preferably until the fourth character. Thus, the clocking of shiftregister 457 is preferably enabled at the beginning of the fourthcharacter of the transmitted pseudo video scan line after the 12th linecounted (line 11) of the displayed row is started. As was previouslymentioned, the output of gate 991 is preferably applied to the presetinput of flip-flop 1002 via path 997 (FIG. 3). The Q output of flip-flop983 is also preferably connected in parallel to one input of another twoinput NAND gate 999 whose other input is connected through an inverterto the output of gate 985. Gate 999 preferably produces a negative levelduring the 12th line counted (line 11) which terminates a hold period.This 12th line counted is the time during which data is preferablywritten into the main memory 1030 through 1042 (FIG. 13). The low levelat the output of gate 999 is preferably applied to the main memorycontrol (read) line 446 via a two input NOR gate 1001, whose other inputis the inverted erase signal, through an inverter 1003. Gate 1001preferably causes the memory control read line 446 to also go low duringan erase cycle as a result of the inverted erase input applied thereto.As was described in out previous U.S. Pat. No. 3,889,054, the output ofgate 994 which is provided through an inverter 996 preferably generatesthe memory pulse R/W via path 995 which is provided to the memory 1030through 1042 through inverter 1047 and gate 1046 via path 1044 (FIG.13). Thus, the operation of the update control circuit 979 preferablyprevents any possible flicker in the display during the main memorywrite mode. The balance of the circuit of FIG. 12 is preferablyidentical with that described with reference to FIG. 11 of our previousU.S. Pat. No. 3,889,054 with the exception of the differences previouslynoted above.

COMPUTER/PRINTER CRT DISPLAY INTERFACE

Referring now to FIGS. 24 and 25, the computer/printer CRT displayinterface 8004 which was generally referred to with reference to FIG. 26with respect to the option of utilizing a printer to provide hard copytext in addition to the video display of information shall be describedin greater detail. As was previously mentioned, the above describedsystem will function as an improved row grabbing terminal 28 without theadditional computer/printer CRT display interface 8004 and printer 8006,if such hard copy text material is not desired, without departing fromthe spirit and scope of the present invention. However, assuming suchhard copy text is desired, the computer/printer interface 8004 shall nowbe described with reference to FIGS. 24 and 25. As will be described ingreater detail hereinafter, the interface 8004 preferably utilizescharacter information when available at a high speed rate so as toenable continuous high speed video display of the information which isnormally preferably provided with the improved row grabbing terminal 28of the present invention, as well as with out previously described rowgrabbing terminal described in U.S. Pat. No. 3,889,054, while alsoenabling real time pick off of this information for printing. Theprinter 8006 is preferably a conventional matrix printer, such as anExtel Model No. AF11, whose operations are preferably controlled by themicroprocessor 6000. The following functions are preferably commanded bythe microprocessor 6000: PRINTER WRITE, PRINT, LINE FEED, CARRIAGERETURN, SPACE COMMAND, and the 32/64 CHARACTER COMMAND, as indicated bythe control lines illustrated in FIGS. 24 and 26. The PRINTER WRITECOMMAND from the microprocessor, provided via path 1007 frommicroprocessor 6000, preferably causes the printer interface 8004 towrite a row of characters into a buffer memory 1011 from the terminalmain memory 1030 through 1042 as will be described in greater detailhereinafter. The PRINT COMMAND, provided via path 1013 frommicroprocessor 6000, causes the interface 8004 to output the row ofcharacters to the printer 8006 at the proper baud rate for the printer8006, such as at 110 baud, in serieal EIA standard format includingstart and stop bits for the printer 8006. The LINE FEED COMMAND,provided via path 1015 from microprocessor 6000, preferably causes theinterface 8004 to issue an ASCII line feed character to the printer 8006in the same format as the characters; that is, in serial EIA standardformat at the same rate, such as the 110 baud rate. The CARRIAGE RETURNCOMMAND, provided via path 1017 from microprocessor 6000, preferablycauses the interface 8004 to issue an ASCII carriage return character tothe printer 8006 in the same format as the characters. The SPACECOMMAND, provided via path 1019 from the microprocessor 6000, preferablycauses the interface 8004 to issue an ASCII space character to theprinter 8006 in the same format as the characters. The 32/64 CHARACTERCOMMAND, provided via path 1021 from microprocessor 6000 to interface8004, preferably causes the interface 8004 to write into its memory 1011the correct number of characters. Thus, as will be described in greaterdetail hereinafter, the microprocessor 6000 can establish each printedpage format.

Now describing the memory write mode for the interface 8004. When theinterface 8004 receives a PRINTER WRITE COMMAND via path 1007, thissignal is provided to the clock input of a flip-flop 1023 which isclocked to a set state. This causes a second fip-flop 1025 tosubsequently be clocked to its set state by the first horizontal syncpulse occurring after flip-flop 1023 is clocked to its set state. Whenflip-flop 1025 is set, its Q or inverted output preferably resets orclears flip-flop 1023 via path 1023a. The set output of flip-flop 1025preferably operates a conventional multiplexer 1027, such as a TexasInstruments SN74157N which is illustratively represented in FIG. 25 byfurther illustrating its various sections 1027a, 1027b, 1027c and 1027das switches which are located in FIG. 25 in their appropriate functionalpositions for purposes of clarity. Thus, the operation of multiplexer1027 preferably puts the interface 8004 into the write mode. Multiplexersection 1027d connects the horizontal sync pulse to the clock input of aconventional bit counter 1029 which will therefore advance one count foreach TV line after the start of the write cycle. The write cyclepreferably lasts for eight horizontal lines. During each of the eighthorizontal lines, one bit from the main memory 1030 through 1042 of eachcharacter is preferably written into the buffer memory 1011. Thus, forexample, for line one, no bit is selected; for line two, bit 7 for everycharacter in line two is selected; for line three, bit 6 for everycharacter in line three is selected; for line four, bit 5 for everycharacter in line four is selected; for line five, bit 4 for everycharacter in line five is selected; for line six, bit 3 for everycharacter in line six is selected; for line seven, bit 2 for everycharacter in line seven is selected; and for line eight, bit 2 for everycharacter in line seven is again selected; however, it is inverted. Aconventional bit select multiplexer 1031 preferably selects theappropriate main memory stage 1030 through 1042 line for each of theeight counts. During the first count, no line is selected if there areonly 7 bits per character. During the second count, the memory linecorresponding to the 7th bit is selected. This process continues foreach line with the memory line for the second bit being selected on theseventh count. As was previously mentioned, on the eighth count thememory line for the second bit is again selected, but it is applied tomultiplexer 1031 through an inverter 1033. The purpose of the aboveprocedure is to preferably convert the standard 6 bit ASCII code fromthe main memory 1030 through 1042 into a 7 bit standard ASCII code whichis used by the printer 8006, such conversion preferably beingconventional. The output of multiplexer 1031 is preferably applied tothe D input of a flip-flop 1035 which is clocked by the PRINTER LATCHCLOCK provided via path 1037 from gate 1094 (FIG. 14) and is preferablythe same waveform that operates the character generator 570 (FIG. 14).Flip-flop 1035, as was previously mentioned, is a D flip-flop and, thus,the output follows the input but is delayed by an amount determined bythe PRINTER LATCH CLOCK 1037. The purpose of flip-flop 1035 is topreferably provide a logic level which is stable for the full characterperiod to the buffer memory 1011. The clocking of memory 1011 ispreferably accomplished via R/W line 1039 through multiplexer section1027a which is shown in the write position in FIG. 25, this signal beinga clock signal provided by multiplexer 1041. The select inputs ofmultiplexer 1041 which are 1043a, 1043b and 1043c, peferably selecteither a low or high level to provide a clock waveform via path 1039with a period equal to a character period. The timing of the clockwaveform 1039 is preferably such that data is clocked in memory 1011after the data has been loaded into the flip-flop 1035. Memory 1011 ispreferably a one-by-1024 bit static random access memory. Thus, itpreferably has one data input line and ten address lines with three ofthe address lines preferably being used for the bit address, allowing 8bits per character, and six of the address lines preferably being usedfor the character address, allowing for up to 64 characters, one ofthese character address lines not being utilized when 32 character linesare to be printed as opposed to 64 character lines. The tenth addresslines is preferably not utilized. The bit address for memory 1011preferably comes from the same bit counter that operates the bit selectmultiplexer 1031, while the character address preferably comes from apair of conventional character counters 1045 and 1047. During the writemode of operation, the character counters 1045 and 1047 are preferablyutilized simply as latches to store the character address for the mainmemory 1030 through 1042 and to apply it to the buffer memory 1011. Thecharacter address is strobed into the character counters 1045 and 1047by the PRINTER LATCH CLOCK 1037. The load inut to counters 1045 and 1047is preferably held low during the write mode by flip-flop 1025. Itshould be noted that the bits need only be selected at the characterrate not at the bit rate since a given bit number for each line in thecharacter contains the same information to the character generator inputfor that character; therefore, for example, bit 1 provides the same bit1 information for all nine lines; similarly bit 2 provides the same bit2 information for all nine lines, etc., thus enabling the use of a lowerspeed circuit thereby slowing things down so that the printer can beoperated at normal speed. Thus, the preferred system takes advantage ofthe eight-to-one differential between the bit and character rates suchas, by way of example, in the 64 character mode the bit rate being 10.2megahertz and the character rate being approximately 1.28 megahertz,while in the 32 character mode the bit rate being 5.1 megahertz and thecharacter rate being approximately 0.64 megahertz. Summarizing the abovedescribed memory write cycle, this cycle starts with the bit counter1029 preferably set for bit 1 which corresponds to count 0, thecharacter counters 1045 an 1047 addressing characters 1 through 32 or 1through 64 and writing all zeros into memory 1011. At the start of thenext TV line, the bit address out of counter 1029 is advanced by one andthe character counters 1045 and 1047 again address characters 1 through32 or 1 through 64 depending on whether it is in a 32 character mode ora 64 character mode and write bit 7 into memory 1011. This preferablycontinues through eight counts or bits of the bit counter 1029, writingbits 6, 5, 4, 3, and 2 into memory 1011 as the line changes. At thebeginning of the ninth TV line, the D output of bit counter 1029preferably goes high to the K input of flip-flop 1025 causing flip-flop1025 to be reset at the trailing edge of the horizontal sync pulse. Theresetting of flip-flop 1025 thereby terminates the write mode withflip-flop 1023 having previously been reset after flip-flop 1025 wasset.

Now describing the output mode, which with reference to FIG. 25 is amode in which all multiplexer sections or switches are set at the R orread position, all of these sections or switches being at the W or writeposition in the write mode. The output mode preferably comprises theprint mode, the line feed mode, the carriage return mode and the spacemode. During the output mode, the bit clock is preferably generated by aconventional oscillator 1049 which preferably comprises a conventionalintegrated circuit oscillator such as an NE555V, which is set at afrequency of preferably 110 hertz for the 110 baud rate described aboveby way of example. This corresponds to a print rate of 10 characters persecond using an 11 bit per character format. It should be noted,however, that the printer rate can be set at any desired value merely bychanging the oscillator 1049 rate, although the presently preferredprinter rate is 110 baud. An 11 bit format preferably consists of onestart bit, 7 character bits, one parity bit, which is preferably notutilized, and 2 stop bits. During the output mode, multiplexer 1027 ispreferably not activated and the output of oscillator 1049 is preferablyapplied through multiplexer section 1027d to the clock input of bitcounter 1029, which counter can preferably count up to 16 for theexample given, although counter 1029 preferably operates in a count 11mode. Thus, preferably when the output of counter 1029 is equal tobinary 10, a gate 1051 connected thereto acts as a decoder and applies anegative level to the clear input of counter 1029 through a two inputNOR gate 1053 whose other input is connected to the J output of J-Kflip-flop 1025. Preferably, counter 1029 has a synchronous clear so thatit is cleared to zero on the next clock following count 11. In addition,during the output mode, counter 1029 preferably establishes the bitsequence of the serial line to the printer 8006 with the counter 1029count value 0, corresponding to count one, establishing the printerstart bit and with counter values 1 through 7, corresponding to countstwo through eight, establishing the data bits, count values 9 and 10,corresponding to counts 10 and 11, establishing the printer stop bits,and with count value 8, corresponding to count 9, preferably not beingutilized.

With reference to the print mode, microprocessor 6000 preferablyinitiates a print cycle, as was previously mentioned, by pulsing line1013. This pulse, provided via path 1013, is the PRINT COMMAND andclocks a flip-flop 1055 to its state. The set output of flip-flop 1055is preferably applied to the enable inputs P and T of character counter1045 which then advances when clocked by the D output of bit counter1029. Thus, character counter 1045 advances at count value 8 of the bitcounter 1029 which is the D output of counter 1029. As a result, thememory 1011 is addressed sequentially through the bit and charactervalues that constitute one row. Thus, the output of memory 1011 is aserial bit stream when bits 1 through 8 of character 1 first appear withbits 1 through 8 of subsequent characters following. In each case, bit 1is a zero level and bits 2 through 8 are the bit values of the characterretrieved from memory 1011. The output of memory 1011 is preferablyapplied to one input of a two input NOR gate 1057, the other inputthereto preferably being provided from the reset output of flip-flop1055 which is low during the print mode. Thus the output of gate 1057 isthe inverted bit stream from memory 1011, this inverted bit streampreferably being applied to one input of a negative NAND gate 1059, theother input thereto being low during this print mode so that thenon-inverted bit stream is present at the outputof gate 1059. The outputof gate 1059 is provided as one input to a two input NOR gate 1061, theother input thereto being the D output of bit couner 1029 which ispreferably high during bits 9, 10 and 11. Thus, the output of gate 1061is inverted data including the printer start bit during bits 1 through8, but is a steady low level during bits 9, 10 and 11. The output ofgate 1061 is preferably inverted by an inverter 1063 to provide thefinal serial output through a level changer 1065 to the printer 8006.The output of inverter 1063 preferably has a high level during bit 1,which is the printer start bit, and follows the data during bits 2through 8, with this output being low during bits 9, 10 and 11. Thiscorresponds to the prescribed preferred EIA format for a 0 start bit andtwo 1 stop bits. Level changer 1065, which is also a line driver,preferably generates an output signal such as, by way of example, with+12 volts representing binary 0 and -12 volts representing binary 1,these levels being prescribed by the EIA serial line interface standard.At the end of the row, a decoder 1067 preferably provides a negativelevel to reset flip-flop 1055 with the decoder 1067 preferably beingprogrammed via line or path 1021 from the microprocessor 6000 be settingthe appropriate input levels to provide a negative output in the case ofa 64 character format at count value 64, which is at the beginning ofcount 65 of the character counter 1047, and to provide a negative outputin the 32 character ode at count value 32, which is at the beginning ofcount 33 of character counter 1047. This resetting of flip-flop 1055preferably terminates the print mode.

The microprocessor 6000 can also preferably command a single specialfunction character such as for example LINE FEED, CARRIAGE RETURN orSPACE. Preferably, if the microprocessor 6000 wants a repeated specialfunction character, it must recommand the character after adequate time,such as for example, 0.1 seconds for a 110 baud rate, has elapsed forthe first special function character to have been isued to the printer8006. A multiplexer 1069, such as a Texas Instruments SN74151AN, isprovided which preferably functions as a programmable charactergenerator to provide the proper bit sequence that corresponds to thespecial character which has been requested. The microprocessor 6000commands a line feed preferably by pulsing line 1015 with the LINE FEEDCOMMAND. This clears flip-flop 1071 which is normally in a set statewith flip-flop 1071 setting a low level at bit input 2 of multiplexer1069 via path 1071a, and also sets bit input 4 low via NOR gate 1072,all other bit inputs to multiplexer 1069 preferably being high.Multiplexer 1069 preferably sequentially switches the bit inputs 0through 7 to the output Y under control of the inputs A, B, C from bitcounter 1029. As a result, a serial output is applied from multiplexer1069 to one input of gate 1059. At this time, the other input to gate1059 is preferably a steady low level so that the single character bitstream is provided to the NOR gate 1061. This bit stream is preferablycombined with the stop bits and is applied to the output line to printer8006 from level changer and line driver 1065 in th same manner aspreviously described with respect to the print mode. At the completionof one special character, flip-flop 1071 is preferably reset by the Doutput of bit counter 1029 via multiplexer section or switch 1027c, NANDgate 1073 and inverter 1075, with the output of inverter 1075 preferablybeing connected in parallel to also provide the character clock for themicroprocessor 6000. This preferably completes a line feed cycle.

When a CARRIAGE RETURN COMMAND is requested by the microprocessor 6000,it pulses line 1017 and clears flip-flop 1077 which then sets bit inputnumbers 1, 3 and 4 low to multiplexer 1069, multiplexer 1069 thengenerating a single character return ASCII code in the manner aspreviously described with respect to the LINE FEED code. Flip-flop 1077is also preferably reset in the same manner as previously described withrespect to the LINE FEED by the next character clock from inverter 1075.

When the microprocessor 6000 commands a space by providing the SPACECOMMAND by pulsing line 1019, flip-flop 1079 is cleared which then setsbit input number 6 low to multiplexer 1069 causing multiplexer 1069 tothen generate a single space ASCII code in the same manner as previouslydescribed with respect to LINE FEED. Flip-flop 1079 is also preferablyreset in the same manner as previously described with respect to LINEFEED by the next character clock provided from inverter 1075.

It should be noted that preferably the character counters 1045 and 1047are cleared during either a line feed or carriage return by the lowlevel from NOR gate 1072. Thus, one row connot follow another to printer8006 unless a LINE FEED or CARRIAGE RETURN is issued. However, normallymicroprocessor 6000 will generate such a CARRIAGE RETURN and LINE FEEDbetween each row. Thus, the interface 8004 enables the microprocessor6000 to make the following types of decisions: what row to be printed,how many rows, whether to print a 32 or 64 character row, how muchmarginal space for the row and whether or not extra spaces are to beplaced between rows. These decisions are based on keyboard inputs fromthe operator provided to the microprocessor 6000, and inputs from thetransmitted data in the form of special characters, directed messages oroverride messages provided to the microprocessor 6000. Due to all of theabove, the computer/printer interface 8004 enables a system to have thefollowing capabilities: the operator can print a complete page ofdisplayed information or any selected row or group of rows of displayedinformation; it provides the capability to print an override message,such as an emergency message, without operator involvement as is alsotrue with respect to a directed message; it permits the operator toselect a special print mode wherein a row or page which he has selectedwill be reprinted whenever data on the selected row or page is changedwith operator involvement not being required after initial selection ofthe mode, this operation being activated by a one time per updatespecial character on the updated row; and special messages such asoverride messages can be emphasized by using extra line feeds betweenrows.

Lastly, referring now to FIGS. 29 and 30, with FIG. 30 being amodification to a portion of FIG. 13, a preferred circuit 9000 forproviding a row-by-row determination of 64 character or 32 characterdisplay of a row in the system of the present invention shall bedescribed. This circuit 9000 may be omitted without departing from thespirit and scope of the present invention if such row-by-rowdetermination of 64 or 32 character display is not desired. As shown andpreferred in FIG. 29, assuming such a 64 or 32 character row-by-rowdetermination is desired, the display screen for the display device 2013is preferably considered as comprising two half screen widths with theleft hand half of the screen preferably displaying even rows which arerows 0 through 62, and with the right hand half of the screen preferablydisplaying odd rows, which are rows 1 through 63. It should be notedthat during normal display as previously described, a row is defined asbeing contained in the full screen width; however, in the instance of arow-by-row determination of 64 or 32 character display, it is preferableto consider half of the screen as comprising a row with each row in thisinstance comprising half a message for the pseudo video scan line.Preferably, in determining whether to provide a 32 or 64 characterdisplay for a given row, if 32 characters are contained in the even row,that is rows 0, 2, 4, 6, etc., up to row 62, then only the even rows isdisplayed for the full screen width irrespective of the presence of anodd row in memory. If, however, there are 64 characters contained in theeven row, then both the odd and the even row are displayed. In thepreferred circuit arrangement 9000, no weight is given to the presenceof a 64 or 32 character bit in the odd row, only the presence of thisbit in the even row being considered. As will further be explained ingreater detail, the control of the clock rate determines whether a 32character or 64 character row is displayed, the memory being read twiceas fast for display of a 64 character row as for a normal 32 characterrow, although the write speed for both a 32 and a 64 character row isthe same because of the same speed of transmission in the preferredsystem of the present invention which receives row-by-row or pseudovideo scan line-by-pseudo video scan line. In the system described inour previous U.S. Pat. No. 3,889,054, the 32 or 64 characterdetermination was based on a page-by-page basis and of each row had tohave a 32 character or 64 character bit according to the page sent orthe display screen would flash between 32 character and a 64 characterdisplay effecting the readability of the display. As shown and preferredin FIG. 30, the memory 1030 through 1042 preferably includes anothermemory stage 2000 for the purposes of determining whether the row is tobe a 64 or 32 character row display, memory 2000 only looking at the rowposition and not at the character position. Preferably, the even rowmessage which is contained in row 0, 2, etc., through row 62, includesthe 64/32 character bit. When the characters are loaded into memory 1030through 1042 for the even row, from shift register 466 (FIG. 13), adecoder latch 2002 preferably decodes the 64/32 character bit which isthen loaded or written into memory stage 2000. The row position inmemory stage 2000 is determined by row latch 470 through multiplexer1020. The character position of memory stage 2000 is preferably ignored.On read out, the 64/32 character bit from memory stage 2000 is thenpreferably read into multiplexer 2004 which then makes a switchconnection to gate 1090 (FIG. 14) via path 2004a (FIG. 14) and todivide-by-eight counter 1080 via path 1079 (FIG. 14) to double the clockfrequency of the prime clock to provide for the 64 character row byproper timing. For a 32 character row, multiplexer switch 2004 is leftin the normal position with no output being provided via 2004a and 1079which, as shown in FIG. 14, are in the 32 character position, so thatonly the prime clock non-doubled output is provided for 32 character rowtiming.

Now describing the adjacent odd row message gating although, if desired,the odd row gating can be omitted if the odd row is not transmitted witha 32/64 character bit. Furthermore, the 32/64 character bit in the oddrow message can be discarded in other conventional ways than to bedescribed hereinafter if desired. As shown and preferred, when the oddbit of row latch 470 through multiplexer 1020 is on, indicating thepresence of an odd row, which information is provided via path 2006a toa two input NAND gate 2006, and the system is loading or writing intomemory 1030 through 1042 and stage 2000, as indicated by the presence ofa write signal via path 2006b to gate 2006, the memory location for theodd row in memory stage 2000 is preferably changed to an unused memorylocation and the output of memory stage 2000 to multiplexer switch 2004remains the same as for the previous even row message in that line. Theignoring of the first bit in the digital output of multiplexer 1020(FIG. 13) will always provide the even row input to memory stage 2000.This is accomplished by preferably grounding the first bit row input tomemory stage 2000 from multiplexer 1020. In order to ignore the 64/32character bit when reading the odd row, then when writing the odd row,the 32/64 character bit is referably put in an unused location byenabling this unused location in memory stage 2000 through gate 2006whose input is the first bit position from row latch register 470, whichis always preferably a 1 for the odd numbers and a 0 for the evennumbers. Therefore, gate 2006 is enabled only when the input providedvia path 2006a is a 1 and the write mode, also indicated by a 1, isprovided via 2006b or, in other words, only for an odd row.

Lastly, discussing erase of memory stage 2000, when the normal erase isprovided to the memory 1030 through 1042, preferably a common spacecharacter is put in all positions of the memory. When the 64 characterrow is erased, in order to insure that this row remains a 64 characterrow or, similarly, for a 32 character row, in order to insure it remainsa 32 character row, in erasing the memory location in memory stage 2000this memory location is positioned to an unused location without erasingthe previously loaded memory bit 2010 from memory stage 2000, the erasesignal via path 2008 together with the row input determining thelocation in memory 2000.

It should be noted that the description of the balance of the circuitrydisclosed herein relating to the row grabbing system 10 which is commonto our previous U.S. Pat. No. 3,889,054, and which has not been repeatedherein, is specifically incorporated by reference herein and theidentical reference numerals therefor are utilized herein for clarity.Furthermore, any other disclosed circuitry not specifically described indetail herein is conventional and readily understandable by one ofordinary skill in the art without further explanation and, accordingly,will not be described in further detail. In addition, it is to beunderstood that all logic described herein is conventional unlessotherwise specified.

By utilizing the improved row grabbing system of the present inventionin which grabbed frames may be updated on a row-to-row basis,conventional television transmission techniques and distributionequipment can be utilized for transmission and reception of data whichhas been packed into pseudo video scan lines which look like aconventional TV scan line to television equipment but contain a completepacket of information suitable for display of an entire row of videoinformation with enhanced noise immunity to any jitter or noise presenton each received pseudo video scan line being processed as well as clockphase correction for the receiver terminal on every data transition ofthe received pseudo video scan line whereby the received informationwill be essentially noise insensitive.

It is to be understood that the above described embodiments of theinvention are merely illustrative of the principles thereof and thatnumerous modifications and embodiments of the invention may be derivedwithin the spirit and scope thereof.

What is claimed is:
 1. A real time frame grabbing system forsubstantially instantaneously providing a continuous video display of aselectable predetermined video frame of information on a video displaymeans from continuously transmittable video information comprising meansfor transmitting said video information as a plurality of pseudo videoscan lines, each of said pseudo video scan lines having a televisionvideo scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide anentire displayable row of video data characters, said pseudo video scanline having an associated transmission time equivalent to saidtelevision video scanline, said packet of digital information comprisingat least address information for said displayable row and datainformation for said displayable characters in said displayable row,each of said pseudo video scan lines further comprising a horizontalsync signal at the beginning thereof and a start bit pulse between saidhorizontal sync signal and said packet of digital information, saidhorizontal sync signal providing a record separator between adjacentpsuedo video scan lines, said transmitting means further comprisingmeans for providing a vertical sync signal .[.signal.]. after apredetermined plurality of pseudo video scan lines have beentransmitted, said pseudo video scan line being a composite video signal,said system further comprising television signal distribution means fordistributing said transmitted composite pseudo video scan line signalsto said video display means for providing said continuous video displayand receiver means operatively connected between said television signaldistribution means and said video display means for processing saiddistributed composite pseudo video scan line signals and capable ofproviding a displayable video row signal to said video display meansfrom each of said pseudo video scan line signals pertaining to saidselected frame for providing said .[.containing.]. .Iadd.continuous.Iaddend.video display, .[.a predetermined plurality of displayablevideo rows comprising a displayable video frame of information,.]. saidstart bit pulse providing a unique synchronizing pulse for eachtransmitted pseudo video scan line for enabling precise determination ofa sampling time for the received distributed pseudo video scan line toenable accurate determination of the binary state of the bits comprisingsaid digital information packet, said receiver signal processing meanscomprising means responsive to the occurrence of said bit .Iadd.and saidhorizontal sync signal .Iaddend.for each distributed pseudo video scanline for providing a reset signal for resetting said processing means inresponse to detection of said start bit .Iadd.for enhancing immunity ofsaid system to any noise or jitter present in said horizontal syncsignal, .Iaddend.whereby noise immunity and accurate signal informationdetection are enhanced.
 2. A real time frame grabbing system inaccordance with claim 1 wherein said processing means start bitresponsive means .[.comprise means.]. responsive to the occurrence ofsaid horizontal sync signal and said start bit for each distributedpseudo video scan line .Iadd.comprises means .Iaddend.for delaying saidhorizontal sync signal a predetermined time inverval determined by theoccurrence of the trailing edge of said horizontal sync signal and theleading edge of said start bit, said delayed horizontal sync signalcomprising said reset signal, whereby immunity of said system to anynoise or jitter present in said horizontal sync signal is enhanced.
 3. Areal time frame grabbing system in accordance with claim 1 wherein saidreceiver signal processing means comprises means for providing a masterclock signal output in accordance with said start bit pulse, and decodermeans operatively connected to said master clock signal output forproviding timing control signals for said receiver signal processingmeans indicative of predetermined character positions within said pseudovideo scan line signal and predetermined bit positions with a characterfor processing said distributed pseudo video scan line to provide saiddisplayable video row signal therefrom.
 4. A real time frame grabbingsystem in accordance with claim 1 wherein said receiver means comprisesmeans for updating said continuously video displayable selectable frameon a displayable video row-by-row basis dependent on the real time datainformation content of said received pseudo video scan lines.
 5. A realtime frame grabbing system in accordance with claim 4 wherein saidupdating means comprises memory means for retrievably storing saidcontinuously distributed pseudo video scan line data portion forproviding said displayable video row therefrom, said memory meansretrievably stored data portion being continuously updateable as saiddata portion of said pseudo video scan line signal associated therewithis updated.
 6. A real time frame grabbing system in accordance withclaim 1 wherein said composite pseudo video scan line signal provided bysaid transmitting means comprises a three level signal having first,second and third signal levels with said digital data information andsaid start bit pulse varying between said second and third signallevels, and said horizontal sync signal information being providedbetween said first and second signal levels.
 7. A real time framegrabbing system in accordance with claim 1 wherein each of said packetsof digital information further cmprises an error check informationcontent based on said data information content for said displayablecharacters of an associated pseudo video scan line, said receiver signalprocessing means comprising error check means for obtaining an errorcheck indication from said distributed associated pseudo video scan lineand comparing said error check indication with said error checkinformation content of said associated pseudo video scan line inaccordance with a predetermined error check condition for providing apredetermined output condition signal when said error check condition issatisfied, said receiver signal processing means further comprisingcondition responsive means operatively connected to said error checkmeans to receive said predetermined output condition signal therefromwhen provided, said condition responsive means inhibiting the provisionof said displayable video row from said associated pseudo video scanline signal when said predetermined output cooling signal is notprovided thereto.
 8. A real time frame grabbing system in accordancewith claim 7 wherein said error check means comprises means for seriallyadding said displayable characters on a word-by-word basis for providingsaid error check condition.
 9. A real time frame grabbing system inaccordance with claim 7 wherein said receiver means comprisesprogrammable microprocessor means for controlling the operation thereof,said microprocessor means comprising means for testing said addressinformation portion of said distributed pseudo video scan line signalfor satisfaction of at least one predetermined signal receptioncondition, said microprocessor means providing a predetermined outputcondition when said reception condition is satisfied; saidmicroprocessor means further comprising memory means for retrievablystoring said pseudo video scan line data portion for providing saiddisplayable video row therefrom, delay means for delaying the storing ofsaid distributed pseudo video scan line signal data portion for asufficient interval to enable testing for said error check condition andtesting of said address information prior to storing of said pseudovideo scan line data portion and said condition responsive means, saidcondition responsive means being further operatively connected to saidaddress information testing means for inhibiting the storage of saiddata portion in said memory means when said predetermined outputcondition signals from said testing means are not provided thereto,whereby the provision of said displayable video tow from said associatedpseudo video scan line signal is inhibited.
 10. A real time framegrabbing system in accordance with claim 9 wherein said receiver meansfurther comprises keyboard means operatively connected to saidmicroprocessor means for selecting said predetermined video frame to becontinuously displayed said address information comprising informationcorresponding to the frame associated with said distributed pseudo videoscan line, said address information testing means comprising means fortesting said frame information, said reception condition beingcorrespondence between said frame information and said selected frame.11. A real time frame grabbing system in accordance with claim 9 whereina predetermined pseudo video scan line signal contains permissioninformation representative of predetermined frames which a video displaymeans is authorized to receive for video display thereof, said receivermeans comprising means for storing said authorized frames, said addressinformation comprising information corresponding to the frame associatedwith said distributed pseudo video scan line, said address informationtesting means comprising means for testing said frame information, saidreception condition being correspondence between said frame informationand stored authorized frame.
 12. A real time frame grabbing system inaccordance with claim 1 wherein said system further comprisesprogrammable means for receiving said continuously transmittable videoinformation, retrievably storing said information, reformatting saidstored information into a desired psuedo video scan line format andcontinuously providing this reformatted information to said transmittingmeans .[.a word at a time, said word comprising a pair of displayablecharacters.]..
 13. A real time frame grabbing system in accordance withclaim 12 wherein said programmable means includes means for interleavingsaid reformatted pseudo video scan line information to provide pseudovideo scan line information corresponding to a common assigned row for aplurality of frames to said transmitting means before providing pseudovideo scan line information corresponding to a subsequent differentcommon assigned row for said plurality of frames to said transmittingmeans.
 14. A real time frame grabbing system in accordance with claim 3wherein said processing means further comprises means responsive to eachtransition in said digital data content of each pseudo video scan linefor continuously correcting the phase of said master clock signal.
 15. Areal time frame grabbing system for substantially instantaneouslyproviding a continuous video display of a selectable predetermined videoframe of information on a video display means from a plurality of pseudovideo scan lines, each of said pseudo video scan lines having atelevision video scan line format and capable of comprising a completeself-contained packet of digital information sufficient to provide anentire displayable row of video data characters, said pseudo video scanline having an associated transmission time equivalent to said televisonvideo scan line, said packet of digital information comprising at leastaddress information for said displayable row and data information forsaid displayable characters in said displayable row, each of said pseudovideo scan lines further comprising a horizontal sync signal at thebeginning thereof and a start bit pulse between said horizontal syncsignal and said packet of digital information, said horizontal syncsignal providing a record separator between adjacent pseudo video scanlines, said pseudo video scan line being a composite video signal, saidsystem comprising means for selecting said predetermined video frame tobe continuously displayed and means operatively connected to said videodisplay means and said frame selection means for processing saidcomposite pseudo video scan line signals and capable of providing adisplayable video row signal to said video display means from each ofsaid pseudo video scan line signals pertaining to said selected framefor providing said continuous video display, .[.a predeterminedplurality of displayable video rows comprising a displayable video frameof information,.].+ said start bit pulse providing a uniquesynchronization pulse for each pseudo video scan line for enablingprecise determination of a sampling time for each pseudo video scan lineto enable accurate determination of the binary state of the bitscomprising said digital information packet, said processing meanscomprising means responsive to the occurrence of said start bit.Iadd.and said horizontal sync signal .Iaddend.for each pseudo videoscan line for providing a reset signal for resetting said processingmeans in response to detection of said start bit .Iadd.for enhancingimmunity of said system to any noise or jitter present in saidhorizontal sync signal, .Iaddend.whereby noise immunity and accuratesignal information detection are enhanced.
 16. A real time framegrabbing system in accordance with claim 15 wherein said processingmeans start bit responsive means .[.comprises means.]. responsive to theoccurrence of said horizontal sync signal and said start bit for eachpseudo video scan line .Iadd.comprises means .Iaddend.for delaying saidhorizontal sync signal a predetermined time interval determined by theoccurrence of the trailing edge of said horizontal sync signal and theleading edge of said start bit, said delayed horizontal sync signalcomprising said reset signal, whereby immunity of said system to anynoise or jitter present in the said horizontal sync signal is enhanced.17. A real time frame grabbing system in accordance with claim 15wherein said processing means comprises means for providing a masterclock signal output in accordance with said start bit pulse, and decodermeans operatively connected to said master clock signal output forproviding timing control signals for said processing means indicative ofpredetermined character position within said pseudo video scan linesignal and predetermined bit positions within a character for processingsaid pseudo video scan line to provide said displayable video row signaltherefrom.
 18. A real time frame grabbing system in accordance withclaim 15 wherein said processing means comprises means for updating saidcontinuously video displayable selectable frame on a displayable videorow-by-row basis dependent on the real time data information content ofsaid video scan lines.
 19. A real time frame grabbing system inaccordance with claim 18 wherein said updating means comprises memorymeans for retrievably storing said pseudo video scan line data portionfor providing said displaying video row therefrom, said memory meansretrievably stored data portion being continuously updateable as saiddata portion of said pseudo video scan line signal associated therewithis updated.
 20. A real time frame grabbing system in accordance withclaim 15 wherein each of said packets of digital information furthercomprises an error clock information content based on said datainformation content for said displayable characters of an associatedpseudo video scan line, said processing means comprising error checkmeans for obtaining an error check indication from said associatedpseudo video scan line and comparing said error check indication withsaid error check information content of said associated pseudo videoscan line in accordance with a predetermined error check condition forproviding a predetermined output condition signal when said error checkcondition is satisified, said processing means further comprisingcondition responsive means operatively connected to said error checkmeans to receive said predetermined output condition signal therefromwhen provided, said condition responsive means inhibiting the provisionof said displayable video row from said associated pseudo video scanline signal when said predetermined output condition signal is notprovided thereto.
 21. A real time frame grabbing system in accordancewith claim 20 wherein said error check means comprises means forserially adding said displayable characters on a word-by-word basis forproviding said error check condition.
 22. A real time frame grabbingsystem in accordance with claim 20 wherein said processing meanscomprises programmable microprocessor means for controlling theoperation thereof, said microprocessor means comprising means fortesting said address information portion of said pseudo video scan linesignal for satisfaction of at least one predetermined signal receptioncondition, said microprocessor means providing a predetermined outputcondition when said reception condition is satisfied; saidmicroprocessor means further comprising memory means for retrievablystoring said pseudo video scan line data portion for providing saiddisplayable video row therefrom, delay means for delaying the storing ofsaid pseudo video scan line signal data portion for a sufficientinterval to enable testing for said error check condition and testing ofsaid address information prior to storing of said pseudo video scan linedata portion and said condition responsive means, said conditionresponsive means being further operatively connected to said addressinformation testing means for inhibiting the storage of said dataportion in said memory means when said predetermined output conditionsignals from said testing means are not provided thereto, whereby theprovision of said displayable video row from said associated pseudovideo scan line signal is inhibited.
 23. A real time frame grabbingsystem in accordance with claim 22 wherein said processing means furthercomprises keyboard means operatively connected to said microprocessormeans for selecting said predetermined video frame to be continuouslydisplayed, said address information comprising information correspondingto the frame associated with said pseudo video scan line, said addressinformation testing means comprising means for testing said frameinformation, said reception condition being correspondence between saidframe information and said selected frame.
 24. A real time framegrabbing system in accordance with claim 22 wherein a predeterminedpseudo video scan line signal contains permission informationrepresentative of predetermined frames which a video display means isauthorized to receive for video display thereof, said processing meeanscomprising means for storing said authorized frames, said addressinformation comprising information corresponding to the frame associatedwith said pseudo video scan line, said address information testing meanscomprising means for testing said frame information, said receptionconditions being correspondence between said frame information andstored authorized frame.
 25. A real time frame grabbing system inaccordance with claim 17 wherein said processing means further comprisesmeans responsive to each transition in said digital data content of eachpseudo video scan line for continuously correcting the phase of saidmaster clock signal. .Iadd.
 26. A real time frame grabbing system inaccordance with claim 12 wherein said programmable means comprises meansfor continuously providing said reformatted information to saidtransmitting means a word at a time, said word comprising a pair ofdisplayable characters. .Iaddend. .Iadd.27. A real time frame grabbingsystem in accordance with claim 1 wherein said receiver means comprisesmeans for updating said continuously video displayable selectable frameon a displayable video row-by-row basis as said data portion of any ofsaid displayable distributed pseudo video scan line signals pertainingto said selected frame is updated. .Iaddend. .Iadd.28. A real time framegrabbing system in accordance with claim 15 wherein said receiver meanscomprises means for updating said continuously video displayableselectable frame on a displayable video row-by-row basis as said dataportion of any of said displayable distributed pseudo video scan linesignals pertaining to said selected frame is updated..Iaddend. .Iadd.29.A real time frame grabbing system in accordance with claim 1 whereinsaid receiver means comprises means for providing a displayable frame ofinformation to said video display means from a predetermined pluralityof displayable video rows..Iaddend. .Iadd.30. A real time frame grabbingsystem in accordance with claim 15 wherein said processing meanscomprises means for providing a displayable frame of information to saidvideo display means from a predetermined plurality of displayable videorows..Iaddend. .Iadd.31. A real time frame grabbing system in accordancewith claim 1 wherein said start bit pulse comprises a single bitpulse..Iaddend. .Iadd.32. A real time frame grabbing system inaccordance with claim 31 wherein said receiver signal processing meanscomprises means for providing a master clock signal output in accordancewith said start bit pulse, and decoder means operatively connected tosaid master clock signal output for providing timing control signals forsaid receiver signal processing means indicative of predeterminedcharacter positions within said pseudo video scan line signal andpredetermined bit positions within a character for processing saiddistributed pseudo video scan line to provide said displayable video rowsignal therefrom..Iaddend. .Iadd.33. A real time frame grabbing systemin accordance with claim 32 wherein said processing means furthercomprises means responsive to each transition in said digital datacontent of each pseudo video scan line for continuously correcting thephase of said master clock signal..Iaddend.